Inventor · disambiguated record
Chiakang Sung
Also filed as: SUNG CHIAKANG
194 granted patents·3 pending applications·4,876 citations·filing 1986–2016
99Inventor score
Top patents by PatentIndex Score
197 records- 0199US7525360B1I/O duty cycle and skew controlALTERA CORP·Filed 2007·Granted Apr 28, 2009·117 cites·20 claims
- 0298US6686769B1Programmable I/O element circuit for high speed logic devicesALTERA CORP·Filed 2001·Granted Feb 3, 2004·146 cites·29 claims
- 0398US6433579B1Programmable logic integrated circuit devices with differential signaling capabilitiesALTERA CORP·Filed 2001·Granted Aug 13, 2002·136 cites·50 claims
- 0498US5828229AProgrammable logic array integrated circuitsALTERA CORP·Filed 1997·Granted Oct 27, 1998·185 cites·3 claims
- 0597US9099999B1Adjustable drive strength input-output buffer circuitryWANG BONNIE I·Filed 2012·Granted Aug 4, 2015·44 cites·14 claims
- 0697US7221193B1On-chip termination with calibrated driver strengthALTERA CORP·Filed 2005·Granted May 22, 2007·67 cites·24 claims
- 0797US6292116B1Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuitALTERA CORP·Filed 2000·Granted Sep 18, 2001·115 cites·20 claims
- 0897US5909126AProgrammable logic array integrated circuit devices with interleaved logic array blocksALTERA CORP·Filed 1996·Granted Jun 1, 1999·133 cites·43 claims
- 0996US9711189B1On-die input reference voltage with self-calibrating duty cycle correctionWANG BONNIE I·Filed 2011·Granted Jul 18, 2017·37 cites·12 claims
- 1096US7593273B2Read-leveling implementations for DDR3 applications on an FPGAALTERA CORP·Filed 2007·Granted Sep 22, 2009·44 cites·22 claims
- 1196US7417452B1Techniques for providing adjustable on-chip termination impedanceALTERA CORP·Filed 2006·Granted Aug 26, 2008·32 cites·25 claims
- 1296US6825698B2Programmable high speed I/O interfaceALTERA CORP·Filed 2002·Granted Nov 30, 2004·46 cites·38 claims
- 1396US6667641B1Programmable phase shift circuitryALTERA CORP·Filed 2002·Granted Dec 23, 2003·73 cites·27 claims
- 1496US6252419B1LVDS interface incorporating phase-locked loop circuitry for use in programmable logic deviceALTERA CORP·Filed 1999·Granted Jun 26, 2001·113 cites·44 claims
- 1596US6236231B1Programmable logic integrated circuit devices with low voltage differential signaling capabilitiesALTERA CORP·Filed 1999·Granted May 22, 2001·111 cites·16 claims
- 1696US5999015ALogic region resources for programmable logic devicesALTERA CORP·Filed 1997·Granted Dec 7, 1999·128 cites·48 claims
- 1796US5717901AVariable depth and width memory deviceALTERA CORP·Filed 1995·Granted Feb 10, 1998·89 cites·15 claims
- 1895US8610462B1Input-output circuit and method of improving input-output signalsWANG XIAOBAO·Filed 2011·Granted Dec 17, 2013·20 cites·22 claims
- 1995US7994821B1Level shifter circuits and methodsALTERA CORP·Filed 2010·Granted Aug 9, 2011·19 cites·20 claims
- 2095US7973553B1Techniques for on-chip terminationALTERA CORP·Filed 2010·Granted Jul 5, 2011·32 cites·21 claims
- 2195US7227395B1High-performance memory interface circuit architectureALTERA CORP·Filed 2005·Granted Jun 5, 2007·22 cites·29 claims
- 2295US7167023B1Multiple data rate interface architectureALTERA CORP·Filed 2005·Granted Jan 23, 2007·20 cites·47 claims
- 2395US6437650B1Phase-locked loop or delay-locked loop circuitry for programmable logic devicesALTERA CORP·Filed 2001·Granted Aug 20, 2002·56 cites·23 claims
- 2495US5982195AProgrammable logic device architecturesALTERA CORP·Filed 1997·Granted Nov 9, 1999·114 cites·21 claims
- 2594US8630131B1Data strobe enable circuitrySHIAO WILMA·Filed 2012·Granted Jan 14, 2014·35 cites·20 claims
- 2694US7218155B1Techniques for controlling on-chip termination resistance using voltage range detectionALTERA CORP·Filed 2005·Granted May 15, 2007·32 cites·23 claims
- 2794US6911860B1On/off reference voltage switch for multiple I/O standardsALTERA CORP·Filed 2001·Granted Jun 28, 2005·59 cites·26 claims
- 2894US6114915AProgrammable wide-range frequency synthesizerALTERA CORP·Filed 1999·Granted Sep 5, 2000·100 cites·17 claims
- 2993US9111603B1Systems and methods for memory controller reference voltage calibrationWANG XIAOBAO·Filed 2012·Granted Aug 18, 2015·17 cites·20 claims
- 3093US8565034B1Variation compensation circuitry for memory interfaceLU SEAN SHAU-TU·Filed 2011·Granted Oct 22, 2013·31 cites·20 claims
- 3193US8400186B1Techniques for buffering single-ended and differential signalsWANG XIAOBAO·Filed 2012·Granted Mar 19, 2013·15 cites·20 claims
- 3293US8390315B1Configurable input-output (I/O) circuitry with pre-emphasis circuitryWANG XIAOBAO·Filed 2012·Granted Mar 5, 2013·16 cites·12 claims
- 3393US7420386B2Techniques for providing flexible on-chip termination control on integrated circuitsALTERA CORP·Filed 2006·Granted Sep 2, 2008·30 cites·20 claims
- 3493US7116135B2Programmable high speed I/O interfaceALTERA CORP·Filed 2004·Granted Oct 3, 2006·30 cites·45 claims
- 3593US6483886B1Phase-locked loop circuitry for programmable logic devicesALTERA CORP·Filed 1999·Granted Nov 19, 2002·78 cites·39 claims
- 3693US6369624B1Programmable phase shift circuitryALTERA CORP·Filed 1999·Granted Apr 9, 2002·78 cites·26 claims
- 3793US5915017AMethod and apparatus for securing programming data of programmable logic deviceALTERA CORP·Filed 1998·Granted Jun 22, 1999·78 cites·20 claims
- 3892US8593195B1High performance memory interface circuit architectureHUANG JOSEPH·Filed 2012·Granted Nov 26, 2013·8 cites·14 claims
- 3992US7378868B2Modular I/O bank architectureALTERA CORP·Filed 2006·Granted May 27, 2008·24 cites·40 claims
- 4092US7236018B1Programmable low-voltage differential signaling output driverALTERA CORP·Filed 2004·Granted Jun 26, 2007·54 cites·12 claims
- 4192US6825692B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2002·Granted Nov 30, 2004·38 cites·25 claims
- 4292US6806733B1Multiple data rate interface architectureALTERA CORP·Filed 2002·Granted Oct 19, 2004·48 cites·16 claims
- 4392US6670825B1Efficient arrangement of interconnection resources on programmable logic devicesALTERA CORP·Filed 2002·Granted Dec 30, 2003·39 cites·24 claims
- 4492US6469553B1Phase-locked loop circuitry for programmable logic devicesALTERA CORP·Filed 2001·Granted Oct 22, 2002·69 cites·29 claims
- 4592US6373278B1LVDS interface incorporating phase-locked loop circuitry for use in programmable logic deviceALTERA CORP·Filed 2001·Granted Apr 16, 2002·47 cites·35 claims
- 4691US9048823B2Duty cycle distortion correction circuitryALTERA CORP·Filed 2013·Granted Jun 2, 2015·10 cites·19 claims
- 4791US7884619B1Method and apparatus for minimizing skew between signalsALTERA CORP·Filed 2009·Granted Feb 8, 2011·17 cites·7 claims
- 4891US7425844B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2007·Granted Sep 16, 2008·14 cites·24 claims
- 4991US6870413B1Schmitt trigger circuit with adjustable trip point voltagesALTERA CORP·Filed 2001·Granted Mar 22, 2005·47 cites·25 claims
- 5091US6314550B1Cascaded programming with multiple-purpose pinsALTERA CORP·Filed 1998·Granted Nov 6, 2001·57 cites·50 claims
Showing the top 50 of 197 patent records by PatentIndex Score.
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