Inventor · disambiguated record
Dale Morris
Also filed as: MORRIS DALE · MORRIS DALE C · MORRIS DALE CALVIN
57 granted patents·12 pending applications·1,701 citations·filing 1990–2019
99Inventor score
Files withHEWLETT PACKARD DEVELOPMENT CO27HEWLETT PACKARD CO8HEWLETT PACKARD ENTPR DEV LP5MORRIS DALE5INST THE DEV OF EMERGING ARCHI4
Top patents by PatentIndex Score
69 records- 0199US5530751AEmbedded hidden identification codes in digital objectsHEWLETT PACKARD CO·Filed 1994·Granted Jun 25, 1996·380 cites·8 claims
- 0293US8219996B1Computer processor with fairness monitorMORRIS DALE C·Filed 2007·Granted Jul 10, 2012·56 cites·31 claims
- 0389US7080242B2Instruction set reconciliation for heterogeneous symmetric-multiprocessor systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jul 18, 2006·53 cites·17 claims
- 0487US7274825B1Image matching using pixel-depth reduction before image comparisonHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 25, 2007·31 cites·15 claims
- 0584US6550001B1Method and implementation of statistical detection of read after write and write after write hazardsINTEL CORP·Filed 1998·Granted Apr 15, 2003·107 cites·34 claims
- 0684US5859999ASystem for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registersIDEA CORP·Filed 1996·Granted Jan 12, 1999·117 cites·21 claims
- 0783US6631460B1Advanced load address table entry invalidation based on register address wraparoundINST THE DEV OF EMERGING ARCHI·Filed 2000·Granted Oct 7, 2003·47 cites·32 claims
- 0883US5742804AInstruction prefetch mechanism utilizing a branch predict instructionINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Apr 21, 1998·109 cites·12 claims
- 0983US5724538AComputer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computerHEWLETT PACKARD CO·Filed 1996·Granted Mar 3, 1998·108 cites·11 claims
- 1080US6986131B2Method and apparatus for efficient code generation for modulo scheduled uncounted loopsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 10, 2006·31 cites·16 claims
- 1179US9223600B1In-processor dynamic address redirection table for substituting instruction stringsROSS JONATHAN K·Filed 2007·Granted Dec 29, 2015·13 cites·35 claims
- 1279US7340630B2Multiprocessor system with interactive synchronization of local clocksHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 4, 2008·27 cites·10 claims
- 1379US6505296B2Emulated branch effected by trampoline mechanismHEWLETT PACKARD CO·Filed 2000·Granted Jan 7, 2003·28 cites·39 claims
- 1476US7421689B2Processor-architecture for facilitating a virtual machine monitorHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 2, 2008·22 cites·12 claims
- 1574US10474380B2External memory controllerHEWLETT PACKARD DEVELOPMENT CO·Filed 2013·Granted Nov 12, 2019·3 cites·14 claims
- 1673US6799263B1Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be abortedHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Sep 28, 2004·70 cites·20 claims
- 1772US8443171B2Run-time updating of prediction hint instructionsMORRIS DALE·Filed 2004·Granted May 14, 2013·17 cites·28 claims
- 1871US7849327B2Technique to virtualize processor input/output resourcesLEUNG HIN L·Filed 2005·Granted Dec 7, 2010·8 cites·9 claims
- 1971US7103880B1Floating-point data speculation across a procedure call using an advanced load address tableHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 5, 2006·16 cites·38 claims
- 2071US6611910B2Method for processing branch operationsIDEA CORP·Filed 1998·Granted Aug 26, 2003·49 cites·15 claims
- 2170US9990244B2Controlling error propagation due to fault in computing node of a distributed computing systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2013·Granted Jun 5, 2018·3 cites·19 claims
- 2269US9219699B2Computer system with fabric modulesGOLDSTEIN MARTIN·Filed 2010·Granted Dec 22, 2015·2 cites·22 claims
- 2369US9146738B2Interleaving bits of multiple instruction results in a single destination registerMORRIS DALE·Filed 2008·Granted Sep 29, 2015·4 cites·23 claims
- 2469US6286095B1Computer apparatus having special instructions to force ordered load and store operationsHEWLETT PACKARD CO·Filed 1995·Granted Sep 4, 2001·61 cites·8 claims
- 2568US7424597B2Variable reordering (Mux) instructions for parallel table lookups from registersHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 9, 2008·13 cites·15 claims
- 2668US6308261B1Computer system having an instruction for probing memory latencyHEWLETT PACKARD CO·Filed 1998·Granted Oct 23, 2001·51 cites·7 claims
- 2767US9244736B2Thinning operating systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2013·Granted Jan 26, 2016·2 cites·19 claims
- 2866US5915117AComputer architecture for the deferral of exceptions on speculative instructionsINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jun 22, 1999·49 cites·34 claims
- 2964US6931515B2Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loadsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Aug 16, 2005·9 cites·21 claims
- 3063US7680999B1Privilege promotion based on check of previous privilege levelHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 16, 2010·10 cites·24 claims
- 3163US6237077B1Instruction template for efficient processing clustered branch instructionsIDEA CORP·Filed 1997·Granted May 22, 2001·42 cites·7 claims
- 3263US5717616AComputer hardware instruction and method for computing population countsHEWLETT PACKARD CO·Filed 1993·Granted Feb 10, 1998·37 cites·8 claims
- 3360US8505020B2Computer workload migration using processor poolingDE DINECHIN CHRISTOPHE·Filed 2010·Granted Aug 6, 2013·1 cites·14 claims
- 3460US7441104B2Parallel subword instructions with distributed resultsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Oct 21, 2008·6 cites·6 claims
- 3559US7143270B1System and method for adding an instruction to an instruction set architectureHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Nov 28, 2006·7 cites·26 claims
- 3659US7103756B2Data processor with individually writable register subword locationsHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Sep 5, 2006·6 cites·2 claims
- 3758US7523455B2Method and system for application managed context switchingHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 21, 2009·5 cites·15 claims
- 3855US11126372B2External memory controllerHEWLETT PACKARD ENTPR DEV LP·Filed 2019·Granted Sep 21, 2021·0 cites·15 claims
- 3954US6813627B2Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operandsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 2, 2004·4 cites·20 claims
- 4053US10452498B2Fault tolerance for persistent main memoryHEWLETT PACKARD ENTPR DEV LP·Filed 2013·Granted Oct 22, 2019·0 cites·20 claims
- 4153US5928356AMethod and apparatus for selectively controlling groups of registersINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 27, 1999·27 cites·17 claims
- 4252US7281116B2Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodesHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Oct 9, 2007·2 cites·11 claims
- 4351US8452945B2Indirect indexing instructionsMORRIS DALE·Filed 2002·Granted May 28, 2013·2 cites·8 claims
- 4451US6438682B1Method and apparatus for predicting loop exit branchesINTEL CORP·Filed 1998·Granted Aug 20, 2002·23 cites·23 claims
- 4550US9927988B2Data move engine to move a block of dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2013·Granted Mar 27, 2018·0 cites·15 claims
- 4650US7680990B2Superword memory-access instructions for data processorHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 16, 2010·1 cites·13 claims
- 4750US7325228B1Data speculation across a procedure call using an advanced load address tableHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 29, 2008·1 cites·35 claims
- 4849US10817361B2Controlling error propagation due to fault in computing node of a distributed computing systemHEWLETT PACKARD ENTPR DEV LP·Filed 2018·Granted Oct 27, 2020·0 cites·19 claims
- 4948US6079012AComputer that selectively forces ordered execution of store and load operations between a CPU and a shared memoryHEWLETT PACKARD CO·Filed 1997·Granted Jun 20, 2000·22 cites·8 claims
- 5047US7869516B2Motion estimation using bit-wise block comparisons for video compresssionHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 11, 2011·0 cites·11 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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