Inventor · disambiguated record
Srinivasan Iyer
Also filed as: IYER SRINIVASAN · IYER SRINIVASAN VASU
9 granted patents·3 pending applications·63 citations·filing 2012–2023
84Inventor score
Top patents by PatentIndex Score
12 records- 0194US9268528B2System and method for dynamically reducing power consumption of floating-point logicNVIDIA CORP·Filed 2013·Granted Feb 23, 2016·40 cites·20 claims
- 0286US9600235B2Technique for performing arbitrary width integer arithmetic operations using fixed width elementsNVIDIA CORP·Filed 2013·Granted Mar 21, 2017·9 cites·21 claims
- 0382US9465578B2Logic circuitry configurable to perform 32-bit or dual 16-bit floating-point operationsNVIDIA CORP·Filed 2013·Granted Oct 11, 2016·7 cites·20 claims
- 0476US9465575B2FFMA operations using a multi-step approach to data shiftingNVIDIA CORP·Filed 2013·Granted Oct 11, 2016·4 cites·22 claims
- 0566US9829956B2Approach to power reduction in floating-point operationsNVIDIA CORP·Filed 2012·Granted Nov 28, 2017·2 cites·20 claims
- 0652US8909687B2Efficient FIR filtersIYER SRINIVASAN·Filed 2012·Granted Dec 9, 2014·1 cites·24 claims
- 0752US2024291375A1Control architecture and schemes to reduce switching losses in direct current (dc)-dc convertersTEXAS INSTRUMENTS INC·Filed 2023·Application pending·0 cites
- 0849US9383968B2Math processing by detection of elementary valued operandsNVIDIA CORP·Filed 2013·Granted Jul 5, 2016·0 cites·20 claims
- 0948US10503513B2Dispatching a stored instruction in response to determining that a received instruction is of a same instruction typeNVIDIA CORP·Filed 2013·Granted Dec 10, 2019·0 cites·21 claims
- 1046US2015193203A1Efficiency in a fused floating-point multiply-add unitNVIDIA CORP·Filed 2014·Application pending·0 cites
- 1145US11150721B2Providing hints to an execution unit to prepare for predicted subsequent arithmetic operationsNVIDIA CORP·Filed 2012·Granted Oct 19, 2021·0 cites·25 claims
- 1233US2013262819A1Single cycle compare and select operationsIYER SRINIVASAN·Filed 2012·Application pending·0 cites
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