Inventor · disambiguated record
Richard C. Foss
Also filed as: FOSS RICHARD · FOSS RICHARD C
61 granted patents·5 pending applications·1,624 citations·filing 1980–2013
99Inventor score
Top patents by PatentIndex Score
66 records- 0198US6657919B2Delayed locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2003·Granted Dec 2, 2003·75 cites·17 claims
- 0298US6236581B1High voltage boosted word line supply charge pump and regulator for DRAMMOSAID TECHNOLOGIES INC·Filed 2000·Granted May 22, 2001·143 cites·14 claims
- 0398US4789796AOutput buffer having sequentially-switched outputPHILIPS CORP·Filed 1986·Granted Dec 6, 1988·130 cites·14 claims
- 0497US6992950B2Delay locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2003·Granted Jan 31, 2006·111 cites·10 claims
- 0597US5796673ADelay locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 1994·Granted Aug 18, 1998·154 cites·6 claims
- 0696US6657918B2Delayed locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2002·Granted Dec 2, 2003·72 cites·17 claims
- 0793US6067272ADelayed locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 1997·Granted May 23, 2000·54 cites·12 claims
- 0891US6980448B2DRAM boosted voltage supplyMOSAID TECHNOLOGIES INC·Filed 2003·Granted Dec 27, 2005·36 cites·6 claims
- 0989US6314052B2Delayed locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2001·Granted Nov 6, 2001·29 cites·10 claims
- 1088US7266747B2Error correction scheme for memoryMOSAID TECHNOLOGIES INC·Filed 2003·Granted Sep 4, 2007·40 cites·22 claims
- 1188US6205083B1Delayed locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 1999·Granted Mar 20, 2001·41 cites·5 claims
- 1288US5414662ADynamic random access memory using imperfect isolating transistorsMOSAID TECHNOLOGIES INC·Filed 1993·Granted May 9, 1995·61 cites·17 claims
- 1388US5267201AHigh voltage boosted word line supply charge pump regulator for DRAMMOSAID INC·Filed 1991·Granted Nov 30, 1993·62 cites·6 claims
- 1487US7859930B2Embedded memory databus architectureMOSAID TECHNOLOGIES INC·Filed 2009·Granted Dec 28, 2010·9 cites·59 claims
- 1586US6522562B2Content addressable memory cell having improved layoutMOSAID TECHNOLOGIES INC·Filed 2001·Granted Feb 18, 2003·44 cites·11 claims
- 1684US7350137B2Method and circuit for error correction in CAM cellsMOSAID TECHNOLOGIES INC·Filed 2005·Granted Mar 25, 2008·13 cites·22 claims
- 1784US5406523AHigh voltage boosted word line supply charge pump and regulator for DRAMMOSAID TECHNOLOGIES INC·Filed 1993·Granted Apr 11, 1995·47 cites·10 claims
- 1882US4367420ADynamic logic circuits operating in a differential mode for array processingTHOMPSON FOSS INC·Filed 1980·Granted Jan 4, 1983·28 cites·11 claims
- 1979US7636880B2Error correction scheme for memoryMOSAID TECHNOLOGIES INC·Filed 2007·Granted Dec 22, 2009·9 cites·15 claims
- 2078US6661723B2Wide databus architectureMOSAID TECHNOLOGIES INC·Filed 2002·Granted Dec 9, 2003·13 cites·7 claims
- 2177US6888730B2Content addressable memory cellMOSAID TECHNOLOGIES INC·Filed 2002·Granted May 3, 2005·26 cites·7 claims
- 2277US6751111B2High density memory cellMOSAID TECHNOLOGIES INC·Filed 2002·Granted Jun 15, 2004·23 cites·14 claims
- 2377US5828620AHigh voltage boosted word line supply charge pump and regulator for DRAMMOSAID TECHNOLOGIES INC·Filed 1997·Granted Oct 27, 1998·30 cites·24 claims
- 2476US5742544AWide databus architectureMOSAID TECHNOLOGIES INC·Filed 1994·Granted Apr 21, 1998·18 cites·6 claims
- 2576US4786830ACMOS input buffer circuit for TTL signalsPHILIPS CORP·Filed 1987·Granted Nov 22, 1988·22 cites·8 claims
- 2675US6055201AHigh voltage boosted word line supply charge pump and regulator for DRAMMOSAID TECHNOLOGIES INC·Filed 1998·Granted Apr 25, 2000·20 cites·20 claims
- 2774US5497115AFlip-flop circuit having low standby power for driving synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 1994·Granted Mar 5, 1996·34 cites·6 claims
- 2872US7095666B2Wide databus architectureMOSAID TECHNOLOGIES INC·Filed 2003·Granted Aug 22, 2006·9 cites·22 claims
- 2972US5699313AHigh voltage boosted word line supply charge pump and regulator for dramMOSAID TECHNOLOGIES INC·Filed 1996·Granted Dec 16, 1997·24 cites·28 claims
- 3071US6366491B1Wide databus architectureMOSAID TECHNOLOGIES INC·Filed 2001·Granted Apr 2, 2002·9 cites·3 claims
- 3170US7609573B2Embedded memory databus architectureMOSAID TECHNOLOGIES INC·Filed 2008·Granted Oct 27, 2009·3 cites·40 claims
- 3269US6614705B2Dynamic random access memory boosted voltage supplyMOSAID TECHNOLOGIES INC·Filed 2001·Granted Sep 2, 2003·9 cites·6 claims
- 3366US6580654B2Boosted voltage supplyMOSAID TECHNOLOGIES INC·Filed 2002·Granted Jun 17, 2003·8 cites·6 claims
- 3466US5233560ADynamic memory bit line precharge schemeFOSS RICHARD C·Filed 1991·Granted Aug 3, 1993·26 cites·12 claims
- 3565US8441878B2Embedded memory databus architectureFOSS RICHARD C·Filed 2012·Granted May 14, 2013·1 cites·17 claims
- 3664US8218386B2Embedded memory databus architectureFOSS RICHARD C·Filed 2010·Granted Jul 10, 2012·1 cites·18 claims
- 3764US5870329AEnhanced ASIC process cellMOSAID TECHNOLOGIES INC·Filed 1997·Granted Feb 9, 1999·28 cites·15 claims
- 3864US5255232ADRAM cell plate and precharge voltage generatorMOSAID INC·Filed 1991·Granted Oct 19, 1993·23 cites·6 claims
- 3964US4980862AFolded bitline dynamic ram with reduced shared supply voltagesMOSAID INC·Filed 1988·Granted Dec 25, 1990·17 cites·9 claims
- 4060US6580652B2Priority encoder circuit and method for content addressable memoryFiled 2002·Granted Jun 17, 2003·7 cites·13 claims
- 4160US5724304ARepeater with threshold modulationMOSAID TECHNOLOGIES INC·Filed 1996·Granted Mar 3, 1998·12 cites·7 claims
- 4260US5574681AMethod for DRAM sensing current controlMOSAID TECHNOLOGIES INC·Filed 1995·Granted Nov 12, 1996·16 cites·2 claims
- 4358US7599246B2Delay locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2005·Granted Oct 6, 2009·1 cites·22 claims
- 4457US8369182B2Delay locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2009·Granted Feb 5, 2013·1 cites·10 claims
- 4557US6195282B1Wide database architectureMOSAID TECHNOLOGIES INC·Filed 1997·Granted Feb 27, 2001·8 cites·11 claims
- 4656US7486580B2Wide databus architectureMOSAID TECHNOLOGIES INC·Filed 2006·Granted Feb 3, 2009·1 cites·25 claims
- 4756US7010741B2Method and circuit for error correction in CAM cellsMOSAID TECHNOLOGIES·Filed 2002·Granted Mar 7, 2006·7 cites·7 claims
- 4855US8638638B2Delay locked loop implementation in a synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 2013·Granted Jan 28, 2014·0 cites·20 claims
- 4955US6888731B2Method and apparatus for replacing defective rows in a semiconductor memory arrayMOSAID TECHNOLOGIES INC·Filed 2002·Granted May 3, 2005·9 cites·12 claims
- 5054US5245576ADynamic memory row/column redundancy schemeFOSS RICHARD C·Filed 1991·Granted Sep 14, 1993·16 cites·8 claims
Showing the top 50 of 66 patent records by PatentIndex Score.
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