Inventor · disambiguated record
John D. Jabusch
Also filed as: JABUSCH JOHN D · JABUSCH JOHN DAVID
16 granted patents·7 pending applications·814 citations·filing 1988–2011
95Inventor score
Top patents by PatentIndex Score
23 records- 0195US6034956AMethod of simultaneously attempting parallel path connections in a multi-stage interconnection networkIBM·Filed 1998·Granted Mar 7, 2000·175 cites·19 claims
- 0293US5774067AFlash-flooding multi-stage interconnection network with parallel path seeking switching elementsIBM·Filed 1997·Granted Jun 30, 1998·133 cites·19 claims
- 0388US5617547ASwitch network extension of bus architectureIBM·Filed 1996·Granted Apr 1, 1997·155 cites·14 claims
- 0479US6263374B1Apparatus for coupling a bus-based architecture to a switch networkIBM·Filed 1994·Granted Jul 17, 2001·101 cites·20 claims
- 0579US5418916ACentral processing unit checkpoint retry for store-in and store-through cache systemsIBM·Filed 1990·Granted May 23, 1995·87 cites·2 claims
- 0678US7934081B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2006·Granted Apr 26, 2011·8 cites·6 claims
- 0777US7644233B2Apparatus and method for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2006·Granted Jan 5, 2010·8 cites·6 claims
- 0876US5404461ABroadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networksIBM·Filed 1991·Granted Apr 4, 1995·52 cites·19 claims
- 0974US8868976B2System-level testcase generationBEN-YEHUDA SHIMON·Filed 2010·Granted Oct 21, 2014·6 cites·25 claims
- 1073US7996618B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2011·Granted Aug 9, 2011·3 cites·12 claims
- 1168US8386712B2Structure for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2008·Granted Feb 26, 2013·4 cites·8 claims
- 1262US7610449B2Apparatus and method for saving power in a trace cacheIBM·Filed 2006·Granted Oct 27, 2009·2 cites·12 claims
- 1353US5384773AMulti-media analog/digital/optical switching apparatusIBM·Filed 1992·Granted Jan 24, 1995·25 cites·18 claims
- 1451US5742761AApparatus for adapting message protocols for a switch network and a busIBM·Filed 1997·Granted Apr 21, 1998·26 cites·28 claims
- 1550US5786771ASelectable checking of message destinations in a switched parallel networkIBM·Filed 1993·Granted Jul 28, 1998·22 cites·9 claims
- 1642US2008235500A1Structure for instruction cache trace formationDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 1741US2008250206A1Structure for using branch prediction heuristics for determination of trace formation readinessDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 1841US2008250207A1Design structure for cache maintenanceDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 1940US2008215804A1Structure for register renaming in a microprocessorDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 2039US2008120468A1Instruction Cache Trace FormationDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2139US2008077778A1Method and Apparatus for Register Renaming in a MicroprocessorDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2239US2008114964A1Apparatus and Method for Cache MaintenanceDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 2329US4890253APredetermination of result conditions of decimal operationsIBM·Filed 1988·Granted Dec 26, 1989·7 cites·5 claims
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