Inventor · disambiguated record
Markus Buehler
Also filed as: BUEHLER MARKUS · BUEHLER MARKUS T
25 granted patents·4 pending applications·260 citations·filing 2004–2020
94Inventor score
Top patents by PatentIndex Score
29 records- 0199US7308669B2Use of redundant routes to increase the yield and reliability of a VLSI layoutIBM·Filed 2005·Granted Dec 11, 2007·211 cites·40 claims
- 0280US7386815B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2005·Granted Jun 10, 2008·9 cites·17 claims
- 0378US8234594B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameANDERSON BRENT A·Filed 2006·Granted Jul 31, 2012·7 cites·17 claims
- 0470US8407654B2Glitch power reductionBUECHNER THOMAS·Filed 2012·Granted Mar 26, 2013·3 cites·20 claims
- 0569US8015527B2Routing of wires of an electronic circuitIBM·Filed 2008·Granted Sep 6, 2011·5 cites·16 claims
- 0668US7996808B2Computer readable medium, system and associated method for designing integrated circuits with loop insertionsIBM·Filed 2008·Granted Aug 9, 2011·4 cites·8 claims
- 0765US7984394B2Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2007·Granted Jul 19, 2011·3 cites·4 claims
- 0864US7960836B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2008·Granted Jun 14, 2011·2 cites·20 claims
- 0963US8010916B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2008·Granted Aug 30, 2011·2 cites·13 claims
- 1062US8010925B2Method and system for placement of electric circuit components in integrated circuit designIBM·Filed 2008·Granted Aug 30, 2011·2 cites·11 claims
- 1161US8380737B2Computing intersection of sets of numbersIBM·Filed 2011·Granted Feb 19, 2013·2 cites·20 claims
- 1260US8495286B2Write buffer for improved DRAM write access patternsBALKESEN CAGRI·Filed 2010·Granted Jul 23, 2013·3 cites·6 claims
- 1359US8627263B2Gate configuration determination and selection from standard cell libraryBUECHNER THOMAS·Filed 2012·Granted Jan 7, 2014·1 cites·16 claims
- 1459US8612911B2Estimating power consumption of an electronic circuitBUECHNER THOMAS·Filed 2012·Granted Dec 17, 2013·1 cites·20 claims
- 1558US7904861B2Method, system, and computer program product for coupled noise timing violation avoidance in detailed routingIBM·Filed 2007·Granted Mar 8, 2011·2 cites·14 claims
- 1656US7962881B2Via structure to improve routing of wires within an integrated circuitIBM·Filed 2008·Granted Jun 14, 2011·2 cites·21 claims
- 1755US8513663B2Signal repowering chip for 3-dimensional integrated circuitBUEHLER MARKUS·Filed 2010·Granted Aug 20, 2013·1 cites·5 claims
- 1852US11281474B2Partial computer processor core shutoffIBM·Filed 2020·Granted Mar 22, 2022·0 cites·15 claims
- 1948US8032851B2Structure for an integrated circuit design for reducing coupling between wires of an electronic circuitIBM·Filed 2007·Granted Oct 4, 2011·0 cites·10 claims
- 2047US2010257503A1Post-routing coupling fixes for integrated circuitsIBM·Filed 2009·Application pending·0 cites
- 2146US9760669B2Congestion mitigation by wire orderingIBM·Filed 2015·Granted Sep 12, 2017·0 cites·15 claims
- 2246US8756538B2Parsing data representative of a hardware design into commands of a hardware design environmentIBM·Filed 2013·Granted Jun 17, 2014·0 cites·14 claims
- 2346US2006136854A1Method for placement of pipeline latchesIBM·Filed 2004·Application pending·0 cites
- 2445US10831493B2Hardware apparatus to measure memory localityIBM·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 2545US8006208B2Reducing coupling between wires of an electronic circuitIBM·Filed 2010·Granted Aug 23, 2011·0 cites·19 claims
- 2645US7398485B2Yield optimization in router for systematic defectsIBM·Filed 2006·Granted Jul 8, 2008·0 cites·17 claims
- 2744US2008059933A1Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated CircuitIBM·Filed 2007·Application pending·0 cites
- 2841US8731858B2Method and system for calculating timing delay in a repeater network in an electronic circuitBUEHLER MARKUS·Filed 2009·Granted May 20, 2014·0 cites·20 claims
- 2941US2008148213A1Routing method for reducing coupling between wires of an electronic circuitBELAIDI MOUSSADEK·Filed 2007·Application pending·0 cites
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