Inventor · disambiguated record
Franklin M. Baez
Also filed as: BAEZ FRANKLIN · BAEZ FRANKLIN M · BAEZ FRANKLIN MANUEL
10 granted patents·1 pending application·57 citations·filing 1998–2023
85Inventor score
Top patents by PatentIndex Score
11 records- 0182US11775004B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2021·Granted Oct 3, 2023·1 cites·8 claims
- 0275US10756031B1Decoupling capacitor stiffenerIBM·Filed 2019·Granted Aug 25, 2020·2 cites·18 claims
- 0372US12111684B2Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die moduleIBM·Filed 2023·Granted Oct 8, 2024·0 cites·8 claims
- 0467US6958636B2Charge leakage correction circuit for applications in PLLsIBM·Filed 2004·Granted Oct 25, 2005·14 cites·17 claims
- 0562US10949600B2Semiconductor package floating metal checksIBM·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 0656US10423751B2Semiconductor package floating metal checksIBM·Filed 2017·Granted Sep 24, 2019·0 cites·20 claims
- 0756US7176731B2Variation tolerant charge leakage correction circuit for phase locked loopsIBM·Filed 2004·Granted Feb 13, 2007·9 cites·15 claims
- 0850US6327552B2Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curvesINTEL CORP·Filed 1999·Granted Dec 4, 2001·26 cites·15 claims
- 0947US10706204B2Automated generation of surface-mount package designIBM·Filed 2018·Granted Jul 7, 2020·0 cites·17 claims
- 1039US2020075468A1Dedicated Integrated Circuit Chip Carrier Plane Connected to Decoupling Capacitor(s)IBM·Filed 2018·Application pending·0 cites
- 1130US7346479B2Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraintsINTEL CORP·Filed 1998·Granted Mar 18, 2008·5 cites·28 claims
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