Inventor · disambiguated record
Da Zhang
Also filed as: ZHANG DA · Zhang da-zhi
32 granted patents·11 pending applications·527 citations·filing 2002–2023
97Inventor score
Top patents by PatentIndex Score
43 records- 0196US7494856B2Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressorFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 24, 2009·51 cites·20 claims
- 0295US7018901B1Method for forming a semiconductor device having a strained channel and a heterojunction source/drainFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 28, 2006·105 cites·24 claims
- 0393US7927989B2Method for forming a transistor having gate dielectric protection and structureFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 19, 2011·27 cites·8 claims
- 0493US7575975B2Method for forming a planar and vertical semiconductor structure having a strained semiconductor layerFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Aug 18, 2009·34 cites·17 claims
- 0593US7226820B2Transistor fabrication using double etch/refill processFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 5, 2007·34 cites·20 claims
- 0691US7544997B2Multi-layer source/drain stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 9, 2009·52 cites·20 claims
- 0791US7446026B2Method of forming a CMOS device with stressor source/drain regionsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 4, 2008·29 cites·8 claims
- 0890US7238561B2Method for forming uniaxially strained devicesFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 3, 2007·25 cites·19 claims
- 0987US7067868B2Double gate device having a heterojunction source/drain and strained channelFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 27, 2006·39 cites·17 claims
- 1086US7282415B2Method for making a semiconductor device with strain enhancementFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 16, 2007·17 cites·15 claims
- 1183US7727870B2Method of making a semiconductor device using a stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 1, 2010·13 cites·16 claims
- 1281US7763510B1Method for PFET enhancementFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Jul 27, 2010·9 cites·18 claims
- 1381US7687337B2Transistor with differently doped strained current electrode regionFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 30, 2010·13 cites·23 claims
- 1480US7514313B2Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 7, 2009·9 cites·20 claims
- 1579US7833852B2Source/drain stressors formed using in-situ epitaxial growthFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 16, 2010·8 cites·8 claims
- 1679US7572706B2Source/drain stressor and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 11, 2009·7 cites·15 claims
- 1778US7879666B2Semiconductor resistor formed in metal gate stackFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Feb 1, 2011·9 cites·20 claims
- 1877US7883953B2Method for transistor fabrication with optimized performanceFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Feb 8, 2011·7 cites·18 claims
- 1976US7538002B2Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressorsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted May 26, 2009·7 cites·20 claims
- 2075US7858482B2Method of forming a semiconductor device using stress memorizationFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Dec 28, 2010·5 cites·15 claims
- 2175US7615806B2Method for forming a semiconductor structure and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Nov 10, 2009·6 cites·19 claims
- 2274US8039341B2Selective uniaxial stress modification for use with strained silicon on insulator integrated circuitFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 18, 2011·6 cites·8 claims
- 2371US8003454B2CMOS process with optimized PMOS and NMOS transistor devicesFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 23, 2011·3 cites·20 claims
- 2462US8330231B2Transistor having gate dielectric protection and structureZHANG DA·Filed 2011·Granted Dec 11, 2012·1 cites·15 claims
- 2561US6884727B2Semiconductor fabrication process for modifying the profiles of patterned featuresFREESCALE SEMICONDUCTOR INC·Filed 2002·Granted Apr 26, 2005·8 cites·16 claims
- 2660US7479422B2Semiconductor device with stressors and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 20, 2009·2 cites·7 claims
- 2757US8962410B2Transistors with different threshold voltagesZHANG DA·Filed 2011·Granted Feb 24, 2015·1 cites·17 claims
- 2856US2025169106A1Semiconductor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 2955US2024105849A1Semiconductor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3054US2024105521A1Semiconductor device structure with isolation layer and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3153US9812558B2Three-dimensional transistor and methods of manufacturing thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 7, 2017·0 cites·20 claims
- 3250US7800141B2Electronic device including a semiconductor finFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Sep 21, 2010·0 cites·20 claims
- 3348US9627411B2Three-dimensional transistor and methods of manufacturing thereofUNIV NAT TAIWAN·Filed 2015·Granted Apr 18, 2017·0 cites·20 claims
- 3444US7413970B2Process of forming an electronic device including a semiconductor finFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Aug 19, 2008·0 cites·8 claims
- 3541US7795089B2Forming a semiconductor device having epitaxially grown source and drain regionsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 14, 2010·0 cites·13 claims
- 3641US2009289280A1Method for Making Transistors and the Device ThereofZHANG DA·Filed 2008·Application pending·0 cites
- 3738US2007184600A1Stressed-channel CMOS transistorsFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 3836US2013102143A1Method of making a non-volatile memory cell having a floating gateZHANG DA·Filed 2011·Application pending·0 cites
- 3936US2004211661A1Method for plasma deposition of a substrate barrier layerFiled 2003·Application pending·0 cites
- 4035US2005196961A1Method for forming a semiconductor device having metal silicideFiled 2004·Application pending·0 cites
- 4134US2003203615A1Method for depositing barrier layers in an openingFiled 2002·Application pending·0 cites
- 4234US2006030093A1Strained semiconductor devices and method for forming at least a portion thereofZHANG DA·Filed 2004·Application pending·0 cites
- 4334US2006115949A1Semiconductor fabrication process including source/drain recessing and fillingFREESCALE SEMICONDUCTOR INC·Filed 2004·Application pending·0 cites
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