Inventor · disambiguated record
Amitay Levi
Also filed as: LEVI AMITAY
63 granted patents·10 pending applications·742 citations·filing 2001–2022
98Inventor score
Files withSPIN MEMORY INC28SILICON STORAGE TECH INC16INTEGRATED SILICON SOLUTION CAYMAN INC11SPIN TRANSFER TECH4SPIN TRANSFER TECH INC3
Top patents by PatentIndex Score
73 records- 0197US7927994B1Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturingSILICON STORAGE TECH INC·Filed 2010·Granted Apr 19, 2011·73 cites·6 claims
- 0297US7868375B2Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturingSILICON STORAGE TECH INC·Filed 2009·Granted Jan 11, 2011·230 cites·2 claims
- 0395US10333063B1Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymersSPIN MEMORY INC·Filed 2018·Granted Jun 25, 2019·6 cites·20 claims
- 0495US7315056B2Semiconductor memory array of floating gate memory cells with program/erase and select gatesSILICON STORAGE TECH INC·Filed 2004·Granted Jan 1, 2008·106 cites·7 claims
- 0593US10355045B1Three dimensional perpendicular magnetic junction with thin-film transistorSPIN MEMORY INC·Filed 2017·Granted Jul 16, 2019·9 cites·21 claims
- 0693US10192789B1Methods of fabricating dual threshold voltage devicesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·8 cites·25 claims
- 0792US10679685B2Shared bit line array architecture for magnetoresistive memorySPIN MEMORY INC·Filed 2017·Granted Jun 9, 2020·8 cites·20 claims
- 0892US10236075B1Predicting tunnel barrier endurance using redundant memory structuresSPIN TRANSFER TECH INC·Filed 2017·Granted Mar 19, 2019·12 cites·20 claims
- 0992US8148768B2Non-volatile memory cell with self aligned floating and erase gates, and method of making sameDO NHAN·Filed 2008·Granted Apr 3, 2012·26 cites·8 claims
- 1090US10937479B1Integration of epitaxially grown channel selector with MRAM deviceSPIN MEMORY INC·Filed 2019·Granted Mar 2, 2021·5 cites·12 claims
- 1190US7149110B2Seek window verify program system and method for a multilevel non-volatile memory integrated circuit systemSILICON STORAGE TECH INC·Filed 2003·Granted Dec 12, 2006·54 cites·27 claims
- 1289US10186551B1Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)SPIN TRANSFER TECH INC·Filed 2018·Granted Jan 22, 2019·6 cites·14 claims
- 1388US10957370B1Integration of epitaxially grown channel selector with two terminal resistive switching memory elementSPIN MEMORY INC·Filed 2019·Granted Mar 23, 2021·4 cites·11 claims
- 1488US10658425B2Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channelsSPIN MEMORY INC·Filed 2018·Granted May 19, 2020·5 cites·12 claims
- 1587US10468293B2Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channelsSPIN MEMORY INC·Filed 2017·Granted Nov 5, 2019·5 cites·20 claims
- 1687US6855980B2Semiconductor memory array of floating gate memory cells with low resistance source regions and high source couplingSILICON STORAGE TECH INC·Filed 2003·Granted Feb 15, 2005·35 cites·8 claims
- 1786US10192787B1Methods of fabricating contacts for cylindrical devicesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·5 cites·15 claims
- 1886US7227217B2Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturingSILICON STORAGE TECH INC·Filed 2005·Granted Jun 5, 2007·12 cites·15 claims
- 1986US6727545B2Semiconductor memory array of floating gate memory cells with low resistance source regions and high source couplingSILICON STORAGE TECH INC·Filed 2001·Granted Apr 27, 2004·36 cites·7 claims
- 2083US10192788B1Methods of fabricating dual threshold voltage devices with stacked gatesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·6 cites·18 claims
- 2183US8962493B2Magnetic random access memory cells having improved size and shape characteristicsLEVI AMITAY·Filed 2010·Granted Feb 24, 2015·7 cites·15 claims
- 2282US10192984B1Dual threshold voltage devices with stacked gatesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·6 cites·12 claims
- 2382US7829404B2Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gatesSILICON STORAGE TECH INC·Filed 2007·Granted Nov 9, 2010·8 cites·11 claims
- 2481US8384147B2High endurance non-volatile memory cell and arraySILICON STORAGE TECH INC·Filed 2011·Granted Feb 26, 2013·6 cites·17 claims
- 2580US10629649B2Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistorSPIN MEMORY INC·Filed 2017·Granted Apr 21, 2020·3 cites·24 claims
- 2677US10438999B2Annular vertical Si etched channel MOS devicesSPIN MEMORY INC·Filed 2017·Granted Oct 8, 2019·2 cites·8 claims
- 2775US10355047B1Fabrication methods of forming annular vertical SI etched channel MOS devicesSPIN MEMORY INC·Filed 2017·Granted Jul 16, 2019·2 cites·6 claims
- 2875US6566706B1Semiconductor array of floating gate memory cells and strap regionsSILICON STORAGE TECH INC·Filed 2001·Granted May 20, 2003·13 cites·38 claims
- 2974US12069964B2Three dimensional perpendicular magnetic tunnel junction with thin film transistor arrayINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2022·Granted Aug 20, 2024·0 cites·14 claims
- 3073US7851846B2Non-volatile memory cell with buried select gate, and method of making sameSILICON STORAGE TECH INC·Filed 2008·Granted Dec 14, 2010·5 cites·18 claims
- 3172US8138524B2Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made therebyKOTOV ALEXANDER·Filed 2006·Granted Mar 20, 2012·6 cites·34 claims
- 3272US7816723B2Semiconductor memory array of floating gate memory cells with program/erase and select gatesSILICON STORAGE TECH INC·Filed 2007·Granted Oct 19, 2010·4 cites·4 claims
- 3371US11688649B2Compact and efficient CMOS inverterINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2022·Granted Jun 27, 2023·0 cites·20 claims
- 3470US11626407B2DRAM with selective epitaxial cell transistorINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2022·Granted Apr 11, 2023·0 cites·19 claims
- 3570US11417829B2Three dimensional perpendicular magnetic tunnel junction with thin film transistor arrayINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2018·Granted Aug 16, 2022·2 cites·14 claims
- 3670US10319424B1Adjustable current selectorsSPIN MEMORY INC·Filed 2018·Granted Jun 11, 2019·2 cites·12 claims
- 3770US10243021B1Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)SPIN MEMORY INC·Filed 2017·Granted Mar 26, 2019·1 cites·20 claims
- 3868US10460778B2Perpendicular magnetic tunnel junction memory cells having shared source contactsSPIN MEMORY INC·Filed 2017·Granted Oct 29, 2019·2 cites·9 claims
- 3968US10431628B2Dual channel/gate vertical field-effect transistor (FET) for use with a perpendicular magnetic tunnel junction (PMTJ)SPIN MEMORY INC·Filed 2018·Granted Oct 1, 2019·1 cites·15 claims
- 4068US10347822B1Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devicesSPIN MEMORY INC·Filed 2017·Granted Jul 9, 2019·1 cites·14 claims
- 4167US10497415B2Dual gate memory devicesSPIN MEMORY INC·Filed 2018·Granted Dec 3, 2019·2 cites·11 claims
- 4263US11302697B2DRAM with selective epitaxial cell transistorINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Apr 12, 2022·0 cites·15 claims
- 4360US11302586B2Compact and efficient CMOS inverterINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Apr 12, 2022·0 cites·6 claims
- 4460US10770561B2Methods of fabricating dual threshold voltage devicesSPIN MEMORY INC·Filed 2019·Granted Sep 8, 2020·0 cites·15 claims
- 4560US7084453B2Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectricSILICON STORAGE TECH INC·Filed 2004·Granted Aug 1, 2006·7 cites·13 claims
- 4659US10355046B1Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)SPIN MEMORY INC·Filed 2017·Granted Jul 16, 2019·1 cites·19 claims
- 4758US6969687B2Method of planarizing a semiconductor dieSILICON STORAGE TECH INC·Filed 2004·Granted Nov 29, 2005·5 cites·19 claims
- 4853US11444123B2Selector transistor with metal replacement gate wordlineINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted Sep 13, 2022·0 cites·18 claims
- 4953US9054029B2Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cellsCROCUS TECHNOLOGY INC·Filed 2014·Granted Jun 9, 2015·0 cites·14 claims
- 5052US11329048B2DRAM with selective epitaxial transistor and buried bitlineINTEGRATED SILICON SOLUTION CAYMAN INC·Filed 2020·Granted May 10, 2022·0 cites·19 claims
Showing the top 50 of 73 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →