Inventor · disambiguated record
Gad Sheaffer
Also filed as: SHEAFFER GAD · SHEAFFER GAD S · Sheaffer Gad Shlomo
91 granted patents·19 pending applications·1,436 citations·filing 1995–2017
99Inventor score
Top patents by PatentIndex Score
110 records- 0196US8407425B2Obscuring memory access patterns in conjunction with deadlock detection or avoidanceGUERON SHAY·Filed 2007·Granted Mar 26, 2013·44 cites·13 claims
- 0296US7437581B2Method and apparatus for varying energy per instruction according to the amount of available parallelismINTEL CORP·Filed 2004·Granted Oct 14, 2008·138 cites·50 claims
- 0395US8095824B2Performing mode switching in an unbounded transactional memory (UTM) systemGRAY JAN·Filed 2009·Granted Jan 10, 2012·82 cites·20 claims
- 0493US8886894B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2012·Granted Nov 11, 2014·15 cites·18 claims
- 0591US8250331B2Operating system virtual memory management for hardware transactional memoryYAMADA KOICHI·Filed 2009·Granted Aug 21, 2012·24 cites·7 claims
- 0690US8209689B2Live lock free priority scheme for memory transactions in transactional memoryRAIKIN SHLOMO·Filed 2007·Granted Jun 26, 2012·24 cites·18 claims
- 0789US7587584B2Mechanism to exploit synchronization overhead to improve multithreaded performanceINTEL CORP·Filed 2005·Granted Sep 8, 2009·31 cites·25 claims
- 0889US6957321B2Instruction set extension using operand bearing NOP instructionsINTEL CORP·Filed 2002·Granted Oct 18, 2005·48 cites·38 claims
- 0988US5710902AInstruction dependency chain indentifierINTEL CORP·Filed 1995·Granted Jan 20, 1998·149 cites·9 claims
- 1086US8688951B2Operating system virtual memory management for hardware transactional memoryYAMADA KOICHI·Filed 2012·Granted Apr 1, 2014·8 cites·14 claims
- 1186US8161247B2Wait loss synchronizationGRAY JAN·Filed 2009·Granted Apr 17, 2012·16 cites·13 claims
- 1286US6715064B1Method and apparatus for performing sequential executions of elements in cooperation with a transformINTEL CORP·Filed 2000·Granted Mar 30, 2004·48 cites·23 claims
- 1384US8140773B2Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STMSAHA BRATIN·Filed 2007·Granted Mar 20, 2012·11 cites·29 claims
- 1483US8516201B2Protecting private data from cache attacksRAIKIN SHLOMO·Filed 2007·Granted Aug 20, 2013·12 cites·13 claims
- 1583US8402218B2Efficient garbage collection and exception handling in a hardware accelerated transactional memory systemGRAY JAN·Filed 2009·Granted Mar 19, 2013·11 cites·18 claims
- 1683US8365016B2Performing mode switching in an unbounded transactional memory (UTM) systemINTEL CORP·Filed 2011·Granted Jan 29, 2013·7 cites·20 claims
- 1783US8316194B2Mechanisms to accelerate transactions using buffered storesADL-TABATABAI ALI-REZA·Filed 2009·Granted Nov 20, 2012·8 cites·5 claims
- 1882US8688917B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2012·Granted Apr 1, 2014·6 cites·18 claims
- 1981US9164923B2Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platformSHEAFFER GAD·Filed 2011·Granted Oct 20, 2015·5 cites·22 claims
- 2081US8812796B2Private memory regions and coherence optimizationsGRAY JAN·Filed 2009·Granted Aug 19, 2014·9 cites·20 claims
- 2181US8806101B2Metaphysical address space for holding lossy metadata in hardwareSHEAFFER GAD·Filed 2008·Granted Aug 12, 2014·10 cites·12 claims
- 2280US9785462B2Registering a user-handler in hardware for transactional memory event handlingSHEAFFER GAD·Filed 2008·Granted Oct 10, 2017·10 cites·34 claims
- 2380US8627017B2Read and write monitoring attributes in transactional memory (TM) systemsSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·8 cites·25 claims
- 2479US9658880B2Efficient garbage collection and exception handling in a hardware accelerated transactional memory systemMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2013·Granted May 23, 2017·4 cites·20 claims
- 2579US5909573AMethod of branch prediction using loop countersINTEL CORP·Filed 1996·Granted Jun 1, 1999·87 cites·7 claims
- 2677US9350909B2Remotely controlled crowd-sourced media captureEMPIRE TECHNOLOGY DEV LLC·Filed 2013·Granted May 24, 2016·3 cites·29 claims
- 2777US8799582B2Extending cache coherency protocols to support locally buffered dataSHEAFFER GAD·Filed 2008·Granted Aug 5, 2014·8 cites·27 claims
- 2877US7613908B2Selective hardware lock disablingINTEL CORP·Filed 2007·Granted Nov 3, 2009·7 cites·12 claims
- 2976US9195600B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2014·Granted Nov 24, 2015·2 cites·20 claims
- 3075US9280397B2Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadataADL-TABATABAI ALI-REZA·Filed 2009·Granted Mar 8, 2016·8 cites·56 claims
- 3175US8769212B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2012·Granted Jul 1, 2014·3 cites·13 claims
- 3275US7958320B2Protected cache architecture and secure programming paradigm to protect applicationsINTEL CORP·Filed 2007·Granted Jun 7, 2011·5 cites·19 claims
- 3375US6055630ASystem and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline unitsINTEL CORP·Filed 1998·Granted Apr 25, 2000·73 cites·23 claims
- 3474US8370577B2Metaphysically addressed cache metadataMICROSOFT CORP·Filed 2009·Granted Feb 5, 2013·6 cites·17 claims
- 3574US8356166B2Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriersMICROSOFT CORP·Filed 2009·Granted Jan 15, 2013·6 cites·15 claims
- 3673US9619298B2Scheduling computing tasks for multi-processor systems based on resource requirementsEMPIRE TECHNOLOGY DEV LLC·Filed 2013·Granted Apr 11, 2017·3 cites·23 claims
- 3773US8521995B2Handling operating system (OS) transitions in an unbounded transactional memory (UTM) modeYAMADA KOICHI·Filed 2009·Granted Aug 27, 2013·5 cites·18 claims
- 3873US6594754B1Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping countersINTEL CORP·Filed 1999·Granted Jul 15, 2003·63 cites·24 claims
- 3972US9003421B2Acceleration threads on idle OS-visible thread execution unitsGABOR RON·Filed 2005·Granted Apr 7, 2015·6 cites·20 claims
- 4071US6965962B2Method and system to overlap pointer load cache missesINTEL CORP·Filed 2002·Granted Nov 15, 2005·15 cites·19 claims
- 4171US5790822AMethod and apparatus for providing a re-ordered instruction cache in a pipelined microprocessorINTEL CORP·Filed 1996·Granted Aug 4, 1998·58 cites·29 claims
- 4270US9100938B2Digital relay for out of network devicesUR SHMUEL·Filed 2012·Granted Aug 4, 2015·2 cites·22 claims
- 4370US8473921B2Debugging mechanisms in a cache-based memory isolation systemTAILLEFER MARTIN·Filed 2009·Granted Jun 25, 2013·5 cites·20 claims
- 4470US7007187B1Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-oversINTEL CORP·Filed 2000·Granted Feb 28, 2006·13 cites·6 claims
- 4569US7454601B2N-wide add-compare-select instructionINTEL CORP·Filed 2002·Granted Nov 18, 2008·14 cites·26 claims
- 4668US8856466B2Mechanisms to accelerate transactions using buffered storesINTEL CORP·Filed 2012·Granted Oct 7, 2014·1 cites·19 claims
- 4768US8627014B2Memory model for hardware attributes within a transactional memory systemSHEAFFER GAD·Filed 2008·Granted Jan 7, 2014·3 cites·29 claims
- 4868US8392929B2Leveraging memory isolation hardware technology to efficiently detect race conditionsTAILLEFER MARTIN·Filed 2009·Granted Mar 5, 2013·4 cites·33 claims
- 4968US6732257B1Reducing the length of lower level instructions by splitting and recombining an immediateINTEL CORP·Filed 2000·Granted May 4, 2004·13 cites·18 claims
- 5067US6944750B1Pre-steering register renamed instructions to execution unit associated locations in instruction cacheINTEL CORP·Filed 2000·Granted Sep 13, 2005·12 cites·31 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
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