Inventor · disambiguated record
Chu-Yun Fu
Also filed as: FU CHU-YUN
46 granted patents·4 pending applications·1,766 citations·filing 1998–2017
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG35YU CHEN-HUA4TAIWAN SEMICONDUCTOR MFG CO LTD3CHANG CHENG-HUNG2LEE TZE-LIANG2
Top patents by PatentIndex Score
50 records- 0198US6037018AShallow trench isolation filled by high density plasma chemical vapor depositionTAIWAN SEMICONDUCTOR MAUFACTUR·Filed 1998·Granted Mar 14, 2000·378 cites·18 claims
- 0297US8440517B2FinFET and method of fabricating the sameLIN HUNG-TA·Filed 2010·Granted May 14, 2013·263 cites·20 claims
- 0397US6316348B1High selectivity Si-rich SiON etch-stop layerTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Nov 13, 2001·175 cites·4 claims
- 0496US7612405B2Fabrication of FinFETs with multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 3, 2009·55 cites·20 claims
- 0595US7118987B2Method of achieving improved STI gap fill with reduced stressTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 10, 2006·109 cites·24 claims
- 0694US6214698B1Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layerTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Apr 10, 2001·108 cites·37 claims
- 0792US9716091B2Fin field effect transistorTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jul 25, 2017·5 cites·20 claims
- 0891US9209300B2Fin field effect transistorTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Dec 8, 2015·8 cites·20 claims
- 0991US8809940B2Fin held effect transistorTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 19, 2014·8 cites·20 claims
- 1089US9379215B2Fin field effect transistorTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Jun 28, 2016·4 cites·20 claims
- 1188US6174818B1Method of patterning narrow gate electrodeTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 16, 2001·77 cites·15 claims
- 1285US7119404B2High performance strained channel MOSFETs by coupled stress effectsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 10, 2006·35 cites·27 claims
- 1384US10269616B2Method of fabricating semiconductor device isolation structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·2 cites·20 claims
- 1484US8883597B2Method of fabrication of a FinFET elementCHANG CHENG-HUNG·Filed 2007·Granted Nov 11, 2014·13 cites·12 claims
- 1584US6245669B1High selectivity Si-rich SiON etch-stop layerTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 12, 2001·65 cites·14 claims
- 1681US6479385B1Interlevel dielectric composite layer for insulation of polysilicon and metal structuresTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Nov 12, 2002·25 cites·14 claims
- 1779US6884736B2Method of forming contact plug on silicide structureTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 26, 2005·20 cites·43 claims
- 1879US6174808B1Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOSTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jan 16, 2001·55 cites·32 claims
- 1978US7611963B1Method for forming a multi-layer shallow trench isolation structure in a semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Nov 3, 2009·8 cites·8 claims
- 2078US6444566B1Method of making borderless contact having a sion buffer layerTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 3, 2002·22 cites·6 claims
- 2177US6426272B1Method to reduce STI HDP-CVD USG deposition induced defectsTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jul 30, 2002·24 cites·26 claims
- 2274US6063711AHigh selectivity etching stop layer for damascene processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 16, 2000·47 cites·23 claims
- 2372US6497993B1In situ dry etching procedure to form a borderless contact holeTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Dec 24, 2002·19 cites·23 claims
- 2471US8110890B2Method of fabricating semiconductor device isolation structureYU CHEN-HUA·Filed 2007·Granted Feb 7, 2012·2 cites·19 claims
- 2569US6207483B1Method for smoothing polysilicon gate structures in CMOS devicesTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Mar 27, 2001·12 cites·3 claims
- 2669US6090714AChemical mechanical polish (CMP) planarizing trench fill method employing composite trench fill layerTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jul 18, 2000·34 cites·6 claims
- 2768US6261957B1Self-planarized gap-filling by HDPCVD for shallow trench isolationTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 17, 2001·35 cites·15 claims
- 2867US6274514B1HDP-CVD method for forming passivation layers with enhanced adhesionTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 14, 2001·32 cites·13 claims
- 2965US7371629B2N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modificationsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted May 13, 2008·10 cites·14 claims
- 3064US8822293B2Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devicesYU CHEN-HUA·Filed 2008·Granted Sep 2, 2014·2 cites·18 claims
- 3164US8404561B2Method for fabricating an isolation structureLEE TZE-LIANG·Filed 2010·Granted Mar 26, 2013·2 cites·20 claims
- 3262US6423653B1Reduction of plasma damage for HDP-CVD PSG processTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Jul 23, 2002·8 cites·14 claims
- 3360US6365523B1Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layersTAIWAN SEMICONDUCTOR MAUFACTUR·Filed 1998·Granted Apr 2, 2002·25 cites·24 claims
- 3459US6245682B1Removal of SiON ARC film after poly photo and etchTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jun 12, 2001·22 cites·19 claims
- 3557US9673082B2Method of fabricating semiconductor device isolation structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Jun 6, 2017·0 cites·20 claims
- 3656US7098116B2Shallow trench isolation method for reducing oxide thickness variations at different pattern densitiesTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 29, 2006·8 cites·33 claims
- 3756US6713406B1Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devicesTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Mar 30, 2004·5 cites·16 claims
- 3856US6372664B1Crack resistant multi-layer dielectric layer and method for formation thereofTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 16, 2002·20 cites·13 claims
- 3955US9224606B2Method of fabricating semiconductor device isolation structureYU CHEN-HUA·Filed 2011·Granted Dec 29, 2015·0 cites·19 claims
- 4051US6630398B2Borderless contact with buffer layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 7, 2003·3 cites·7 claims
- 4150US6228780B1Non-shrinkable passivation scheme for metal em improvementTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted May 8, 2001·16 cites·16 claims
- 4249US6461966B1Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvementTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·5 cites·40 claims
- 4348US8580653B2Method for fabricating an isolation structureLEE TZE-LIANG·Filed 2013·Granted Nov 12, 2013·0 cites·20 claims
- 4444US7892909B2Polysilicon gate formation by in-situ dopingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 22, 2011·0 cites·20 claims
- 4543US2006049036A1Method and apparatus for real-time control and monitor of deposition processesTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 4641US2008194072A1Polysilicon gate formation by in-situ dopingYU CHEN-HUA·Filed 2007·Application pending·0 cites
- 4740US7297632B2Scratch reduction for chemical mechanical polishingTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 20, 2007·0 cites·21 claims
- 4840US2006157776A1System and method for contact module processingCHANG CHENG-HUNG·Filed 2005·Application pending·0 cites
- 4940US2006024879A1Selectively strained MOSFETs to improve drive currentTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 5034US8173503B2Fabrication of source/drain extensions with ultra-shallow junctionsCHIU YIHANG·Filed 2009·Granted May 8, 2012·0 cites·7 claims
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