Inventor
GOETTING F ERICH
US58 patents
Patents
50 patentsUS7126372B2Oct 24, 2006
Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration
XILINX INC151 citations99
US6289068B1Sep 11, 2001
Delay lock loop with clock phase shifter
XILINX INC169 citations99
US6204687B1Mar 20, 2001
Method and structure for configuring FPGAS
XILINX INC336 citations99
US6191614B1Feb 20, 2001
FPGA configuration circuit including bus-based CRC register
XILINX INC245 citations99
US5744979AApr 28, 1998
FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses
XILINX INC348 citations99
US5365125ANov 15, 1994
Logic cell for field programmable gate array having optional internal feedback and optional cascade
XILINX INC287 citations99
US7499513B1Mar 3, 2009
Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit
XILINX INC83 citations98
US7218137B2May 15, 2007
Reconfiguration port for dynamic reconfiguration
XILINX INC100 citations98
US6441641B1Aug 27, 2002
Programmable logic device with partial battery backup
XILINX INC113 citations98
US6429682B1Aug 6, 2002
Configuration bus interface circuit for FPGAs
XILINX INC83 citations98
US6366117B1Apr 2, 2002
Nonvolatile/battery-backed key in PLD
XILINX INC126 citations98
US6262596B1Jul 17, 2001
Configuration bus interface circuit for FPGAS
XILINX INC116 citations98
US5958026ASep 28, 1999
Input/output buffer supporting multiple I/O standards
XILINX INC96 citations98
US5386154AJan 31, 1995
Compact logic cell for field programmable gate array chip
XILINX INC113 citations98
US7235999B2Jun 26, 2007
System monitor in a programmable logic device
XILINX INC59 citations97
US7187742B1Mar 6, 2007
Synchronized multi-output digital clock manager
XILINX INC71 citations97
US7138820B2Nov 21, 2006
System monitor in a programmable logic device
XILINX INC73 citations97
US6507211B1Jan 14, 2003
Programmable logic device capable of preserving user data during partial or complete reconfiguration
XILINX INC52 citations96
US6294930B1Sep 25, 2001
FPGA with a plurality of input reference voltage levels
XILINX INC31 citations96
US6204710B1Mar 20, 2001
Precision trim circuit for delay lines
XILINX INC85 citations96
US6049227AApr 11, 2000
FPGA with a plurality of I/O voltage levels
XILINX INC33 citations96
US5877632AMar 2, 1999
FPGA with a plurality of I/O voltage levels
XILINX INC43 citations96
US5367207ANov 22, 1994
Structure and method for programming antifuses in an integrated circuit array
XILINX INC86 citations96
US5349248ASep 20, 1994
Adaptive programming method for antifuse technology
XILINX INC84 citations96
US5291079AMar 1, 1994
Configuration control unit for programming a field programmable gate array and reading array status
XILINX INC70 citations96
US7010014B1Mar 7, 2006
Digital spread spectrum circuitry
XILINX INC39 citations95
US5498979AMar 12, 1996
Adaptive programming method for antifuse technology
XILINX INC52 citations95
US5764534AJun 9, 1998
Method for providing placement information during design entry
XILINX INC30 citations93
US5500608AMar 19, 1996
Logic cell for field programmable gate array having optional internal feedback and optional cascade
XILINX INC41 citations93
US5331226AJul 19, 1994
Logic cell for field programmable gate array having optional input inverters
XILINX INC51 citations93
US5319254AJun 7, 1994
Logic cell which can be configured as a latch without static one's problem
XILINX INC39 citations93
US8001511B1Aug 16, 2011
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
XILINX INC16 citations92
US7599299B2Oct 6, 2009
Dynamic reconfiguration of a system monitor (DRPORT)
XILINX INC35 citations92
US7402443B1Jul 22, 2008
Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes
XILINX INC20 citations92
US7233532B2Jun 19, 2007
Reconfiguration port for dynamic reconfiguration-system monitor interface
XILINX INC26 citations92
US7230445B1Jun 12, 2007
System monitor in a programmable logic device
XILINX INC33 citations92
US6775342B1Aug 10, 2004
Digital phase shifter
XILINX INC28 citations92
US6587534B2Jul 1, 2003
Delay lock loop with clock phase shifter
XILINX INC21 citations92
US6525562B1Feb 25, 2003
Programmable logic device capable of preserving state data during partial or complete reconfiguration
XILINX INC38 citations92
US6448809B2Sep 10, 2002
FPGA with a plurality of input reference voltage levels
XILINX INC14 citations92
US6191613B1Feb 20, 2001
Programmable logic device with delay-locked loop
XILINX INC37 citations92
US6086629AJul 11, 2000
Method for design implementation of routing in an FPGA using placement directives such as local outputs and virtual buffers
XILINX INC70 citations92
US5912937AJun 15, 1999
CMOS flip-flop having non-volatile storage
XILINX INC35 citations92
US7345507B1Mar 18, 2008
Multi-product die configurable as two or more programmable integrated circuits of different logic capacities
XILINX INC27 citations91
US5561367AOct 1, 1996
Structure and method for testing wiring segments in an integrated circuit device
XILINX INC22 citations91
US5617021AApr 1, 1997
High speed post-programming net verification method
XILINX INC19 citations88
US7451421B1Nov 11, 2008
Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies
XILINX INC12 citations84
US7109750B2Sep 19, 2006
Reconfiguration port for dynamic reconfiguration-controller
XILINX INC17 citations84
US6445232B1Sep 3, 2002
Digital clock multiplier and divider with output waveform shaping
XILINX INC19 citations84
US7498192B1Mar 3, 2009
Methods of providing a family of related integrated circuits of different sizes
XILINX INC11 citations83
Showing the top 50 of 58 patents by PatentIndex Score.