Inventor · disambiguated record
Josine Loo
Also filed as: LOO JOSINE · LOO JOSINE JOHANNA GERARDA PETRA
7 granted patents·1 pending application·25 citations·filing 2003–2008
77Inventor score
Top patents by PatentIndex Score
8 records- 0177US8452369B2CMOS compatible microneedle structuresHUYS ROELAND·Filed 2008·Granted May 28, 2013·19 cites·23 claims
- 0263US7838367B2Method for the manufacture of a semiconductor device and a semiconductor device obtained through itNXP BV·Filed 2005·Granted Nov 23, 2010·3 cites·14 claims
- 0359US7407844B2Planar dual gate semiconductor deviceNXP BV·Filed 2005·Granted Aug 5, 2008·2 cites·9 claims
- 0440US7772646B2Method of manufacturing a semiconductor device and such a semiconductor deviceNXP BV·Filed 2005·Granted Aug 10, 2010·0 cites·10 claims
- 0539US7829411B2Method and device to form high quality oxide layers of different thickness in one processing stepNXP BV·Filed 2003·Granted Nov 9, 2010·1 cites·12 claims
- 0638US7795112B2Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channelIMEC·Filed 2005·Granted Sep 14, 2010·0 cites·22 claims
- 0737US2010264492A1Semiconductor on Insulator Semiconductor Device and Method of ManufactureSURDEANU RADU·Filed 2006·Application pending·0 cites
- 0830US7488669B2Method to make markers for double gate SOI processingIMEC INTER UNI MICRO ELECTR·Filed 2005·Granted Feb 10, 2009·0 cites·8 claims
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