Inventor · disambiguated record
Terry Parks
Also filed as: PARKS TERRY · PARKS TERRY J
277 granted patents·17 pending applications·5,440 citations·filing 1985–2022
99Inventor score
Files withVIA TECH INC63IP FIRST LLC55HENRY G GLENN49DELL USA LP39VIA ALLIANCE SEMICONDUCTOR CO LTD39
Top patents by PatentIndex Score
294 records- 0198US5455466AInductive coupling system for power and data transferDELL USA LP·Filed 1993·Granted Oct 3, 1995·457 cites·17 claims
- 0297US8978132B2Apparatus and method for managing a microprocessor providing for a secure execution modeHENRY G GLENN·Filed 2008·Granted Mar 10, 2015·41 cites·24 claims
- 0397US5471225ALiquid crystal display with integrated frame bufferDELL USA LP·Filed 1994·Granted Nov 28, 1995·215 cites·18 claims
- 0496US6571331B2Static branch prediction mechanism for conditional branch instructionsIP FIRST LLC·Filed 2001·Granted May 27, 2003·112 cites·8 claims
- 0595US9389863B2Processor that performs approximate computing instructionsVIA TECH INC·Filed 2014·Granted Jul 12, 2016·30 cites·25 claims
- 0695US8370641B2Initialization of a microprocessor providing for execution of secure codeVIA TECH INC·Filed 2008·Granted Feb 5, 2013·26 cites·27 claims
- 0794US10387366B2Neural network unit with shared activation function unitsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Aug 20, 2019·9 cites·21 claims
- 0894US5530960ADisk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each otherDELL USA LP·Filed 1994·Granted Jun 25, 1996·126 cites·7 claims
- 0994US5261068ADual path memory retrieval system for an interleaved dynamic RAM memory unitDELL USA LP·Filed 1990·Granted Nov 9, 1993·249 cites·32 claims
- 1093US10366050B2Multi-operation neural network unitVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jul 30, 2019·7 cites·22 claims
- 1193US10353862B2Neural network unit that performs stochastic roundingVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jul 16, 2019·8 cites·21 claims
- 1293US9043580B2Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)HENRY G GLENN·Filed 2012·Granted May 26, 2015·21 cites·18 claims
- 1393US8843729B2Microprocessor that fuses MOV/ALU instructionsPARKS TERRY·Filed 2011·Granted Sep 23, 2014·24 cites·26 claims
- 1493US8615799B2Microprocessor having secure non-volatile storage accessHENRY G GLENN·Filed 2008·Granted Dec 24, 2013·17 cites·22 claims
- 1593US8255703B2Atomic hash instructionCRISPIN THOMAS A·Filed 2011·Granted Aug 28, 2012·18 cites·20 claims
- 1693US7663957B2Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessorVIA TECH INC·Filed 2008·Granted Feb 16, 2010·34 cites·38 claims
- 1793US4771276AElectromagnetic touch sensor input system in a cathode ray tube display deviceIBM·Filed 1985·Granted Sep 13, 1988·156 cites·8 claims
- 1892US10552370B2Neural network unit with output buffer feedback for performing recurrent neural network computationsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Feb 4, 2020·5 cites·19 claims
- 1991US10671564B2Neural network unit that performs convolutions using collective shift register among array of neural processing unitsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Jun 2, 2020·7 cites·21 claims
- 2091US9967092B2Key expansion logic using decryption key primitivesVIA TECH INC·Filed 2015·Granted May 8, 2018·10 cites·21 claims
- 2191US7788433B2Microprocessor apparatus providing for secure interrupts and exceptionsVIA TECH INC·Filed 2008·Granted Aug 31, 2010·13 cites·27 claims
- 2290US9891918B2Fractional use of prediction history storage for operating system routinesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Feb 13, 2018·9 cites·20 claims
- 2390US9465432B2Multi-core synchronization mechanismVIA TECH INC·Filed 2014·Granted Oct 11, 2016·10 cites·33 claims
- 2490US8090931B2Microprocessor with fused store address/store data microinstructionCOL GERARD M·Filed 2008·Granted Jan 3, 2012·24 cites·12 claims
- 2589US9503122B1Hardware data compressor that sorts hash chains based on node string match probabilitiesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Nov 22, 2016·9 cites·21 claims
- 2689US7546446B2Selective interrupt suppressionIP FIRST LLC·Filed 2003·Granted Jun 9, 2009·65 cites·30 claims
- 2789US7529912B2Apparatus and method for instruction-level specification of floating point formatVIA TECH INC·Filed 2005·Granted May 5, 2009·21 cites·28 claims
- 2888US9911008B2Microprocessor with on-the-fly switching of decryption keysVIA TECH INC·Filed 2015·Granted Mar 6, 2018·6 cites·15 claims
- 2988US9507404B2Single core wakeup multi-core synchronization mechanismVIA TECH INC·Filed 2014·Granted Nov 29, 2016·5 cites·18 claims
- 3088US8819839B2Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levelsHENRY G GLENN·Filed 2008·Granted Aug 26, 2014·19 cites·24 claims
- 3188US8793803B2Termination of secure execution mode in a microprocessor providing for execution of secure codeHENRY G GLENN·Filed 2008·Granted Jul 29, 2014·9 cites·27 claims
- 3287US9972375B2Sanitize-aware DRAM controllerVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted May 15, 2018·8 cites·20 claims
- 3387US9898291B2Microprocessor with arm and X86 instruction length decodersVIA TECH INC·Filed 2015·Granted Feb 20, 2018·5 cites·22 claims
- 3487US9891927B2Inter-core communication via uncore RAMVIA TECH INC·Filed 2014·Granted Feb 13, 2018·4 cites·19 claims
- 3587US9628111B2Hardware data compressor with multiple string match search hash tables each based on different hash sizeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Apr 18, 2017·7 cites·19 claims
- 3687US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 3787US7917568B2X87 fused multiply-add instructionVIA TECH INC·Filed 2007·Granted Mar 29, 2011·16 cites·15 claims
- 3887US7802078B2REP MOVE string instruction execution by selecting loop microinstruction sequence or unrolled sequence based on flag state indicative of low count repeatVIA TECH INC·Filed 2008·Granted Sep 21, 2010·16 cites·21 claims
- 3987US6895498B2Apparatus and method for target address replacement in speculative branch target address cacheIP FIRST LLC·Filed 2001·Granted May 17, 2005·45 cites·2 claims
- 4087US5619723ASystem for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activitiesDELL USA CORP·Filed 1995·Granted Apr 8, 1997·120 cites·5 claims
- 4186US10409767B2Neural network unit with neural memory and array of neural processing units and sequencer that collectively shift row of data received from neural memoryVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Sep 10, 2019·3 cites·21 claims
- 4286US10380064B2Neural network unit employing user-supplied reciprocal for normalizing an accumulated valueVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Aug 13, 2019·3 cites·14 claims
- 4386US9798898B2Microprocessor with secure execution mode and store key instructionsVIA TECH INC·Filed 2015·Granted Oct 24, 2017·5 cites·19 claims
- 4486US7181596B2Apparatus and method for extending a microprocessor instruction setIP FIRST LLC·Filed 2002·Granted Feb 20, 2007·39 cites·29 claims
- 4586US5959923ADigital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuitDELL USA LP·Filed 1993·Granted Sep 28, 1999·62 cites·21 claims
- 4686US5483260AMethod and apparatus for simplified video monitor controlDELL USA LP·Filed 1993·Granted Jan 9, 1996·72 cites·29 claims
- 4786US5483641ASystem for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activitiesDELL USA LP·Filed 1991·Granted Jan 9, 1996·101 cites·14 claims
- 4886US5432735ATernary storage dynamic RAMDELLUSA L P·Filed 1993·Granted Jul 11, 1995·61 cites·13 claims
- 4985US7975132B2Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessorVIA TECH INC·Filed 2009·Granted Jul 5, 2011·12 cites·25 claims
- 5085US7818358B2Microprocessor with random number generator and instruction for storing random dataIP FIRST LLC·Filed 2006·Granted Oct 19, 2010·8 cites·20 claims
Showing the top 50 of 294 patent records by PatentIndex Score.
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