Inventor · disambiguated record
Guillaume Chabanne
Also filed as: CHABANNE GUILLAUME
5 granted patents·1 pending application·9 citations·filing 2014–2025
71Inventor score
Files withSOITEC SILICON ON INSULATOR6
Top patents by PatentIndex Score
6 records- 0192US10957577B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2017·Granted Mar 23, 2021·7 cites·18 claims
- 0283US12261079B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2023·Granted Mar 25, 2025·0 cites·19 claims
- 0378US2025239483A1Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2025·Application pending·0 cites
- 0472US11728207B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2021·Granted Aug 15, 2023·0 cites·20 claims
- 0565US10672646B2Method for fabricating a strained semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2017·Granted Jun 2, 2020·1 cites·19 claims
- 0657US9799549B2Process for manufacturing a composite structureSOITEC SILICON ON INSULATOR·Filed 2014·Granted Oct 24, 2017·1 cites·12 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →