Inventor · disambiguated record
Massud Aminpur
Also filed as: AMINPUR MASSUD · AMINPUR MASSUD A · AMINPUR MASSUD ABUBAKER
23 granted patents·5 pending applications·343 citations·filing 2000–2011
96Inventor score
Files withADVANCED MICRO DEVICES INC18WARRICK SCOTT2CONLEY WILLARD E1FREESCALE SEMICONDUCTOR INC1FROHBERG KAI1
Top patents by PatentIndex Score
28 records- 0193US7314793B2Technique for controlling mechanical stress in a channel region by spacer removalADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 1, 2008·39 cites·14 claims
- 0293US6482726B1Control trimming of hard mask for sub-100 nanometer transistor gateADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 19, 2002·85 cites·20 claims
- 0388US7517816B2Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stressADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 14, 2009·17 cites·6 claims
- 0488US7309654B2Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectricsADVANCED MICRO DEVICES INC·Filed 2006·Granted Dec 18, 2007·14 cites·29 claims
- 0587US8043951B2Method of manufacturing a semiconductor device and semiconductor device obtainable therewithFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Oct 25, 2011·28 cites·20 claims
- 0683US6555472B2Method of producing a semiconductor device using feature trimmingADVANCED MICRO DEVICES INC·Filed 2001·Granted Apr 29, 2003·30 cites·5 claims
- 0774US8557649B2Method for controlling structure heightVENIGALLA RAJASEKHAR·Filed 2011·Granted Oct 15, 2013·4 cites·5 claims
- 0873US6893956B2Barrier layer for a copper metallization layer including a low-k dielectricADVANCED MICRO DEVICES INC·Filed 2003·Granted May 17, 2005·20 cites·41 claims
- 0973US6699641B1Photosensitive bottom anti-reflective coatingADVANCED MICRO DEVICES INC·Filed 2001·Granted Mar 2, 2004·16 cites·25 claims
- 1072US7256113B1System for forming a semiconductor device and method thereofADVANCED MICRO DEVICES INC·Filed 2002·Granted Aug 14, 2007·19 cites·22 claims
- 1168US7151055B2Technique for forming a gate electrode by using a hard maskADVANCED MICRO DEVICES INC·Filed 2004·Granted Dec 19, 2006·13 cites·17 claims
- 1266US8187978B2Method of forming openings in a semiconductor device and semiconductor deviceWARRICK SCOTT·Filed 2007·Granted May 29, 2012·3 cites·20 claims
- 1366US6828240B2Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuitsADVANCED MICRO DEVICES INC·Filed 2002·Granted Dec 7, 2004·13 cites·18 claims
- 1464US6624035B1Method of forming a hard mask for halo implantsADVANCED MICRO DEVICES INC·Filed 2000·Granted Sep 23, 2003·9 cites·27 claims
- 1562US6569606B1Method of reducing photoresist shadowing during angled implantsADVANCED MICRO DEVICES INC·Filed 2000·Granted May 27, 2003·10 cites·14 claims
- 1661US6727558B1Channel isolation using dielectric isolation structuresADVANCED MICRO DEVICES INC·Filed 2001·Granted Apr 27, 2004·9 cites·26 claims
- 1756US6902870B1Patterning of dielectric with added layers of materials aside from photoresist for enhanced pattern transferADVANCED MICRO DEVICES INC·Filed 2002·Granted Jun 7, 2005·5 cites·15 claims
- 1855US6617219B1Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessorsADVANCED MICRO DEVICES INC·Filed 2001·Granted Sep 9, 2003·4 cites·20 claims
- 1954US8435874B2Method of forming openings in a semiconductor device and a semiconductor device fabricated by the methodWARRICK SCOTT·Filed 2008·Granted May 7, 2013·2 cites·20 claims
- 2048US7005380B2Simultaneous formation of device and backside contacts on wafers having a buried insulator layerADVANCED MICRO DEVICES INC·Filed 2003·Granted Feb 28, 2006·3 cites·29 claims
- 2143US8101524B2Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenchesFROHBERG KAI·Filed 2005·Granted Jan 24, 2012·0 cites·11 claims
- 2243US7763547B2Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectricsGLOBALFOUNDRIES INC·Filed 2005·Granted Jul 27, 2010·0 cites·17 claims
- 2340US2010099255A1Method of forming a contact through an insulating layerCONLEY WILLARD E·Filed 2008·Application pending·0 cites
- 2437US2004217421A1SOI field effect transistor element having an ohmic substrate contactFiled 2003·Application pending·0 cites
- 2537US2004043618A1Method for endpoint detection during etchADVANCED MICRO DEVICES INC·Filed 2002·Application pending·0 cites
- 2636US2003232466A1Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back sideFiled 2002·Application pending·0 cites
- 2736US2003203546A1SOI transistor element having an improved backside contact and method of forming the sameFiled 2002·Application pending·0 cites
- 2835US7087509B1Method of forming a gate electrode on a semiconductor device and a device incorporating sameADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 8, 2006·0 cites·20 claims
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