Inventor · disambiguated record
Peter Edward Chadwick
Also filed as: CHADWICK PETER E · CHADWICK PETER EDWARD
10 granted patents·2 pending applications·155 citations·filing 1975–2006
90Inventor score
Files withZARLINK SEMICONDUCTOR LTD4PLESSEY OVERSEAS2CHADWICK PETER E1DECCA LTD1GEN ELECTRIC CO PLC1
Top patents by PatentIndex Score
12 records- 0185US6844788B2Polar loop transmitterZARLINK SEMICONDUCTOR LTD·Filed 2002·Granted Jan 18, 2005·38 cites·20 claims
- 0277US6917791B2Polar loop transmitterZARLINK SEMICONDUCTOR LTD·Filed 2002·Granted Jul 12, 2005·22 cites·8 claims
- 0367US4908532AQuadrature signals generatorPLESSEY OVERSEAS·Filed 1987·Granted Mar 13, 1990·24 cites·7 claims
- 0466US7657320B2Electronic device with dual purpose inductive elementZARLINK SEMICONDUCTOR AB·Filed 2006·Granted Feb 2, 2010·7 cites·3 claims
- 0561US4628518ARadio receiverPLESSEY OVERSEAS·Filed 1983·Granted Dec 9, 1986·23 cites·9 claims
- 0659US4039953AAutomatic aerial attenuatorDECCA LTD·Filed 1975·Granted Aug 2, 1977·10 cites·3 claims
- 0747US6809585B2Frequency modulation system and methodZARLINK SEMICONDUCTOR LTD·Filed 2003·Granted Oct 26, 2004·5 cites·13 claims
- 0841US5159280ATrue logarithmic amplifier having a variable gain amplifierGEN ELECTRIC CO PLC·Filed 1991·Granted Oct 27, 1992·7 cites·3 claims
- 0940US5557640APhase and amplitude equalization arrangementPLESSEY SEMICONDUCTOR LIMITED·Filed 1994·Granted Sep 17, 1996·13 cites·12 claims
- 1038US2003073419A1Power control in polar loop transmittersZARLINK SEMICONDUCTOR LTD·Filed 2002·Application pending·0 cites
- 1134US5493257AModulator with biasing circuit to minimize output distortionPLESSEY SEMICONDUCTORS LTD·Filed 1994·Granted Feb 20, 1996·6 cites·3 claims
- 1232US2005206575A1Dual polarisation antennaCHADWICK PETER E·Filed 2001·Application pending·0 cites
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