Inventor · disambiguated record
Faye D. Baker
Also filed as: BAKER FAYE · BAKER FAYE D · BAKER FAYE DIANN
9 granted patents·1 pending application·256 citations·filing 1996–2008
90Inventor score
Top patents by PatentIndex Score
10 records- 0197US7503020B2IC layout optimization to improve yieldIBM·Filed 2006·Granted Mar 10, 2009·110 cites·15 claims
- 0286US7823106B2Variable performance ranking and modification in design for manufacturability of circuitsIBM·Filed 2008·Granted Oct 26, 2010·26 cites·20 claims
- 0380US5861330AMethod and structure to reduce latch-up using edge implantsIBM·Filed 1997·Granted Jan 19, 1999·36 cites·6 claims
- 0470US6670283B2Backside protection filmsIBM·Filed 2001·Granted Dec 30, 2003·15 cites·20 claims
- 0564US7818694B2IC layout optimization to improve yieldIBM·Filed 2008·Granted Oct 19, 2010·2 cites·20 claims
- 0662US5874318ADishing and erosion monitor structure for damascene metal processingINTERNATIOAL BUSINESS MACHINES·Filed 1996·Granted Feb 23, 1999·26 cites·3 claims
- 0759US5723874ADishing and erosion monitor structure for damascene metal processingIBM·Filed 1996·Granted Mar 3, 1998·22 cites·17 claims
- 0854US6033949AMethod and structure to reduce latch-up using edge implantsIBM·Filed 1998·Granted Mar 7, 2000·11 cites·8 claims
- 0949US6232639B1Method and structure to reduce latch-up using edge implantsIBM·Filed 1998·Granted May 15, 2001·8 cites·8 claims
- 1042US2008201677A1Integrated Circuit (IC) Chip Input/Output (I/O) Cell Design Optimization Method And IC chip With Optimized I/O CellsBAKER FAYE·Filed 2007·Application pending·0 cites
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