Inventor

KILGARIFF EMMETT M

US69 patents

⚠️ This page may combine multiple inventors who share the name “KILGARIFF EMMETT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KILGARIFF EMMETT M

NVIDIA CORP

Multi-sample surface processing using one sample

Graphics processing system having a virtual texturing array

System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering

System, method and computer program product for texture address operations based on computations involving other textures

Overbright evaluator system and method

Programmable shader having register forwarding for reduced register-file bandwidth consumption

Graphical shader by using delay

Perspective correction computation optimization

Increased scalability in the fragment shading pipeline

Reconfigurable high performance texture pipeline with advanced filtering

Scalable shader architecture

Setting downstream render state in an upstream shader

Block linear memory ordering of texture data

Fragment processor having dual mode register file

Scheduling program instruction execution by using fence instructions

Mid-primitive graphics execution preemption

Order-preserving distributed rasterizer

Method and system for texture instruction demotion optimization

System, method, and computer program product for providing a dynamic display refresh

Transparent antialiased memory access

Caching of adaptively sized cache tiles in a unified L2 cache with surface compression

Real-time hardware-assisted GPU tuning using machine learning

Stereo multi-projection implemented using a graphics processing pipeline

Tiled cache invalidation

Leveraging compression for display buffer blit in a graphics system having an integrated graphics processing unit and a discrete graphics processing unit

On-chip anti-alias resolve in a cache tiling architecture

Partial texture loads

Divergent and non-divergent texture fetches

Partial texture loads

Heuristics for improving performance in a tile based architecture

HAKURA ZIYAD S

Cull before vertex attribute fetch and vertex lighting

Distributed stream output in a parallel processing unit

Calculation of plane equations after determination of Z-buffer visibility

Distributed calculation of plane equations

Distributed vertex attribute fetch

Cull before vertex attribute fetch and vertex lighting

Distributed clip, cull, viewport transform and perspective correction

RHOADES JOHNNY S

Distributing primitives to multiple rasterizers

Distributing primitives to multiple rasterizers

Redistribution of generated geometric primitives

DONOVAN WALTER E

Alpha-to-coverage value determination using virtual samples

LEGAKIS JUSTIN S

Computing tessellation coordinates using dedicated hardware

DANSKIN JOHN M

Interprocessor direct cache writes

KILGARIFF EMMETT M

Hardware-managed virtual buffers using a shared memory for load distribution

GLASCO DAVID B

Compression status caching

MONTRYM JOHN S

Determining a working set of texture maps

MOLNAR STEVEN E

Alpha-to-coverage using virtual samples

KELLEHER BRIAN

Techniques for balancing accesses to memory having different memory types

MCALLISTER DAVID KIRK

Zero-bandwidth clears

MCCORMACK JOEL JAMES

Relaxed coherency between different caches