Inventor · disambiguated record
Ricky C. Hetherington
Also filed as: HETHERINGTON RICKY C · HETHERINGTON RICKY CHARLES
60 granted patents·3,661 citations·filing 1988–2009
99Inventor score
Technology areasG06F
Files withSUN MICROSYSTEMS INC37DIGITAL EQUIPMENT CORP15COMPAQ COMPUTER CORP4KAPIL SANJIV2ORACLE AMERICA INC2
Top patents by PatentIndex Score
60 records- 0196US7685354B1Multiple-core processor with flexible mapping of processor cores to cache banksSUN MICROSYSTEMS INC·Filed 2005·Granted Mar 23, 2010·98 cites·20 claims
- 0296US7487327B1Processor and method for device-specific memory address translationSUN MICROSYSTEMS INC·Filed 2005·Granted Feb 3, 2009·134 cites·36 claims
- 0395US7240160B1Multiple-core processor with flexible cache directory schemeSUN MICROSYSTEMS INC·Filed 2005·Granted Jul 3, 2007·75 cites·21 claims
- 0493US7873776B2Multiple-core processor with support for multiple virtual processorsORACLE AMERICA INC·Filed 2005·Granted Jan 18, 2011·49 cites·17 claims
- 0593US4888679AMethod and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elementsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Dec 19, 1989·151 cites·31 claims
- 0692US8180981B2Cache coherent support for flash in a memory hierarchyKAPIL SANJIV·Filed 2009·Granted May 15, 2012·29 cites·15 claims
- 0792US7370243B1Precise error handling in a fine grain multithreaded multicore processorSUN MICROSYSTEMS INC·Filed 2004·Granted May 6, 2008·72 cites·19 claims
- 0891US6353877B1Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writeCOMPAQ COMPUTER CORP·Filed 2000·Granted Mar 5, 2002·70 cites·14 claims
- 0990US7644221B1System interface unitSUN MICROSYSTEMS INC·Filed 2005·Granted Jan 5, 2010·25 cites·23 claims
- 1090US6145054AApparatus and method for handling multiple mergeable misses in a non-blocking cacheSUN MICROSYSTEMS INC·Filed 1998·Granted Nov 7, 2000·175 cites·20 claims
- 1190US4985825ASystem for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computerDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jan 15, 1991·128 cites·11 claims
- 1289US7587658B1ECC encoding for uncorrectable errorsSUN MICROSYSTEMS INC·Filed 2005·Granted Sep 8, 2009·56 cites·15 claims
- 1389US5222224AScheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jun 22, 1993·163 cites·4 claims
- 1488US5222223AMethod and apparatus for ordering and queueing multiple memory requestsDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jun 22, 1993·100 cites·9 claims
- 1587US6119205ASpeculative cache line write backs to avoid hotspotsSUN MICROSYSTEMS INC·Filed 1997·Granted Sep 12, 2000·135 cites·21 claims
- 1687US5475690ADelay compensated signal propagationDIGITAL EQUIPMENT CORP·Filed 1994·Granted Dec 12, 1995·129 cites·7 claims
- 1786US7716521B1Multiple-core, multithreaded processor with flexible error steering mechanismORACLE AMERICA INC·Filed 2005·Granted May 11, 2010·22 cites·20 claims
- 1886US5125083AMethod and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer systemDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jun 23, 1992·91 cites·16 claims
- 1985US6240502B1Apparatus for dynamically reconfiguring a processorSUN MICROSYSTEMS INC·Filed 1997·Granted May 29, 2001·123 cites·8 claims
- 2083US4982402AMethod and apparatus for detecting and correcting errors in a pipelined computer systemDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jan 1, 1991·84 cites·18 claims
- 2181US7401206B2Apparatus and method for fine-grained multithreading in a multipipelined processor coreSUN MICROSYSTEMS INC·Filed 2004·Granted Jul 15, 2008·29 cites·51 claims
- 2281US5890008AMethod for dynamically reconfiguring a processorSUN MICROSYSTEMS INC·Filed 1997·Granted Mar 30, 1999·99 cites·8 claims
- 2381US4995041AWrite back buffer with error correcting capabilitiesDIGITAL EQUIPMENT CORP·Filed 1989·Granted Feb 19, 1991·68 cites·17 claims
- 2480US7353340B2Multiple independent coherence planes for maintaining coherencySUN MICROSYSTEMS INC·Filed 2005·Granted Apr 1, 2008·11 cites·19 claims
- 2580US6430654B1Apparatus and method for distributed non-blocking multi-level cacheSUN MICROSYSTEMS INC·Filed 1998·Granted Aug 6, 2002·91 cites·21 claims
- 2680US6219723B1Method and apparatus for moderating current demand in an integrated circuit processorSUN MICROSYSTEMS INC·Filed 1999·Granted Apr 17, 2001·77 cites·13 claims
- 2780US5996048AInclusion vector architecture for a level two cacheSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 30, 1999·86 cites·16 claims
- 2880US5285323AIntegrated circuit chip having primary and secondary random access memories for a hierarchical cacheDIGITAL EQUIPMENT CORP·Filed 1993·Granted Feb 8, 1994·96 cites·16 claims
- 2980US5113515AVirtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction bufferDIGITAL EQUIPMENT CORP·Filed 1989·Granted May 12, 1992·67 cites·9 claims
- 3078US7330988B2Method and apparatus for power throttling in a multi-thread processorSUN MICROSYSTEMS INC·Filed 2004·Granted Feb 12, 2008·23 cites·30 claims
- 3177US7398360B2Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processorsSUN MICROSYSTEMS INC·Filed 2005·Granted Jul 8, 2008·9 cites·20 claims
- 3277US6122709ACache with reduced tag information storageSUN MICROSYSTEMS INC·Filed 1997·Granted Sep 19, 2000·81 cites·2 claims
- 3376US6058472AApparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machineSUN MICROSYSTEMS INC·Filed 1997·Granted May 2, 2000·86 cites·20 claims
- 3476US5987594AApparatus for executing coded dependent instructions having variable latenciesSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 16, 1999·73 cites·18 claims
- 3575US6212602B1Cache tag cachingSUN MICROSYSTEMS INC·Filed 1997·Granted Apr 3, 2001·74 cites·7 claims
- 3674US5142631ASystem for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose registerDIGITAL EQUIPMENT CORP·Filed 1989·Granted Aug 25, 1992·54 cites·27 claims
- 3773US5978864AMethod for thermal overload detection and prevention for an intergrated circuit processorSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 2, 1999·53 cites·6 claims
- 3871US7529894B2Use of FBDIMM channel as memory channel and coherence channelSUN MICROSYSTEMS INC·Filed 2005·Granted May 5, 2009·5 cites·17 claims
- 3969US6684299B2Method for operating a non-blocking hierarchical cache throttleSUN MICROSYSTEMS INC·Filed 2001·Granted Jan 27, 2004·12 cites·9 claims
- 4069US6073212AReducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tagsSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 6, 2000·55 cites·24 claims
- 4168US5349651ASystem for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translationDIGITAL EQUIPMENT CORP·Filed 1991·Granted Sep 20, 1994·51 cites·16 claims
- 4265US6006326AApparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependenciesSUN MICROSYSTEMS INC·Filed 1997·Granted Dec 21, 1999·46 cites·20 claims
- 4364US5930819AMethod for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cacheSUN MICROSYSTEMS INC·Filed 1997·Granted Jul 27, 1999·43 cites·14 claims
- 4463US6081873AIn-line bank conflict detection and resolution in a multi-ported non-blocking cacheSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 27, 2000·41 cites·13 claims
- 4563US5999727AMethod for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructionsSUN MICROSYSTEMS INC·Filed 1997·Granted Dec 7, 1999·43 cites·19 claims
- 4663US5948106ASystem for thermal overload detection and prevention for an integrated circuit processorSUN MICROSYSTEMS INC·Filed 1997·Granted Sep 7, 1999·39 cites·9 claims
- 4761US6484240B1Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocolsSUN MICROSYSTEMS INC·Filed 1999·Granted Nov 19, 2002·37 cites·22 claims
- 4860US6128711APerformance optimization and system bus duty cycle reduction by I/O bridge partial cache line writesCOMPAQ COMPUTER CORP·Filed 1996·Granted Oct 3, 2000·34 cites·3 claims
- 4959US9208084B2Extended main memory hierarchy having flash memory for page fault handlingKAPIL SANJIV·Filed 2009·Granted Dec 8, 2015·1 cites·16 claims
- 5059US6052775AMethod for non-intrusive cache fills and handling of load missesSUN MICROSYSTEMS INC·Filed 1997·Granted Apr 18, 2000·34 cites·13 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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