Inventor · disambiguated record
Meikei Ieong
Also filed as: IEONG MEIKEI
88 granted patents·14 pending applications·4,430 citations·filing 2000–2014
99Inventor score
Top patents by PatentIndex Score
102 records- 0199US7723207B2Three dimensional integrated circuit and method of designIBM·Filed 2007·Granted May 25, 2010·277 cites·13 claims
- 0299US7312487B2Three dimensional integrated circuitIBM·Filed 2004·Granted Dec 25, 2007·335 cites·11 claims
- 0399US6821826B1Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafersIBM·Filed 2003·Granted Nov 23, 2004·391 cites·19 claims
- 0498US7678638B2Metal gated ultra short MOSFET devicesIBM·Filed 2008·Granted Mar 16, 2010·121 cites·10 claims
- 0598US7494861B2Method for metal gated ultra short MOSFET devicesIBM·Filed 2008·Granted Feb 24, 2009·121 cites·10 claims
- 0698US7459752B2Ultra thin body fully-depleted SOI MOSFETsIBM·Filed 2006·Granted Dec 2, 2008·283 cites·18 claims
- 0798US7348629B2Metal gated ultra short MOSFET devicesIBM·Filed 2006·Granted Mar 25, 2008·124 cites·7 claims
- 0898US7288445B2Double gated transistor and method of fabricationIBM·Filed 2005·Granted Oct 30, 2007·125 cites·3 claims
- 0998US6492212B1Variable threshold voltage double gated transistors and method of fabricationIBM·Filed 2001·Granted Dec 10, 2002·186 cites·11 claims
- 1098US6271094B1Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitanceIBM·Filed 2000·Granted Aug 7, 2001·245 cites·31 claims
- 1197US7329923B2High-performance CMOS devices on hybrid crystal oriented substratesIBM·Filed 2003·Granted Feb 12, 2008·138 cites·5 claims
- 1297US7041538B2Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2003·Granted May 9, 2006·124 cites·11 claims
- 1397US7023055B2CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bondingIBM·Filed 2003·Granted Apr 4, 2006·127 cites·18 claims
- 1497US7002214B1Ultra-thin body super-steep retrograde well (SSRW) FET devicesIBM·Filed 2004·Granted Feb 21, 2006·160 cites·20 claims
- 1597US6916698B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2004·Granted Jul 12, 2005·139 cites·8 claims
- 1697US6830962B1Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processesIBM·Filed 2003·Granted Dec 14, 2004·134 cites·17 claims
- 1796US7087965B2Strained silicon CMOS on hybrid crystal orientationsIBM·Filed 2004·Granted Aug 8, 2006·97 cites·13 claims
- 1896US6815278B1Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientationsIBM·Filed 2003·Granted Nov 9, 2004·132 cites·17 claims
- 1995US7645650B2Double gated transistor and method of fabricationIBM·Filed 2007·Granted Jan 12, 2010·29 cites·18 claims
- 2095US7244958B2Integration of strained Ge into advanced CMOS technologyIBM·Filed 2004·Granted Jul 17, 2007·82 cites·9 claims
- 2195US6911383B2Hybrid planar and finFET CMOS devicesIBM·Filed 2003·Granted Jun 28, 2005·109 cites·11 claims
- 2294US7291886B2Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETsIBM·Filed 2004·Granted Nov 6, 2007·73 cites·30 claims
- 2394US7098508B2Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientationsIBM·Filed 2004·Granted Aug 29, 2006·88 cites·7 claims
- 2493US6762469B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2002·Granted Jul 13, 2004·68 cites·5 claims
- 2592US7453123B2Self-aligned planar double-gate transistor structureIBM·Filed 2007·Granted Nov 18, 2008·15 cites·1 claims
- 2692US7268377B2Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devicesIBM·Filed 2005·Granted Sep 11, 2007·22 cites·16 claims
- 2791US8080838B2Contact scheme for FINFET structures with multiple FINsCHANG LELAND·Filed 2009·Granted Dec 20, 2011·18 cites·18 claims
- 2891US7388259B2Strained finFET CMOS device structuresIBM·Filed 2002·Granted Jun 17, 2008·61 cites·8 claims
- 2990US7547641B2Super hybrid SOI CMOS devicesIBM·Filed 2007·Granted Jun 16, 2009·15 cites·4 claims
- 3089US7525161B2Strained MOS devices using source/drain epitaxyIBM·Filed 2007·Granted Apr 28, 2009·17 cites·9 claims
- 3189US6677646B2Method and structure of a disposable reversed spacer process for high performance recessed channel CMOSIBM·Filed 2002·Granted Jan 13, 2004·41 cites·9 claims
- 3289US6353249B1MOSFET with high dielectric constant gate insulator and minimum overlap capacitanceINTERNAT BUSINSESS MACHINES CO·Filed 2001·Granted Mar 5, 2002·55 cites·10 claims
- 3388US7485506B2Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETSIBM·Filed 2007·Granted Feb 3, 2009·12 cites·1 claims
- 3488US7387925B2Integration of strained Ge into advanced CMOS technologyIBM·Filed 2007·Granted Jun 17, 2008·12 cites·1 claims
- 3588US7259049B2Self-aligned isolation double-gate FETIBM·Filed 2005·Granted Aug 21, 2007·11 cites·12 claims
- 3686US7384851B2Buried stress isolation for high-performance CMOS technologyIBM·Filed 2005·Granted Jun 10, 2008·11 cites·18 claims
- 3786US7205185B2Self-aligned planar double-gate process by self-aligned oxidationIBM·Filed 2003·Granted Apr 17, 2007·26 cites·18 claims
- 3886US6914303B2Ultra thin channel MOSFETIBM·Filed 2003·Granted Jul 5, 2005·33 cites·4 claims
- 3985US9355887B2Dual trench isolation for CMOS with hybrid orientationsCHAN VICTOR·Filed 2012·Granted May 31, 2016·6 cites·11 claims
- 4085US7091069B2Ultra thin body fully-depleted SOI MOSFETsIBM·Filed 2004·Granted Aug 15, 2006·32 cites·13 claims
- 4185US6946696B2Self-aligned isolation double-gate FETIBM·Filed 2002·Granted Sep 20, 2005·29 cites·18 claims
- 4284US7220626B2Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levelsIBM·Filed 2005·Granted May 22, 2007·10 cites·16 claims
- 4383US7704839B2Buried stress isolation for high-performance CMOS technologyIBM·Filed 2008·Granted Apr 27, 2010·8 cites·26 claims
- 4483US7671421B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsIBM·Filed 2006·Granted Mar 2, 2010·8 cites·13 claims
- 4582US7402466B2Strained silicon CMOS on hybrid crystal orientationsIBM·Filed 2006·Granted Jul 22, 2008·8 cites·1 claims
- 4682US7364958B2CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bondingIBM·Filed 2006·Granted Apr 29, 2008·8 cites·37 claims
- 4781US8158481B2CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materialsCHEN TZE-CHIANG·Filed 2010·Granted Apr 17, 2012·5 cites·8 claims
- 4881US7348611B2Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereofIBM·Filed 2005·Granted Mar 25, 2008·7 cites·16 claims
- 4981US7247569B2Ultra-thin Si MOSFET device structure and method of manufactureIBM·Filed 2003·Granted Jul 24, 2007·20 cites·26 claims
- 5081US7023057B2CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bondingIBM·Filed 2004·Granted Apr 4, 2006·24 cites·17 claims
Showing the top 50 of 102 patent records by PatentIndex Score.
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