Inventor · disambiguated record
Kenneth T. Chin
Also filed as: CHIN KENNETH T · CHIN KENNETH TOM
22 granted patents·1 pending application·861 citations·filing 1997–2020
96Inventor score
Files withCOMPAQ COMPUTER CORP12HEWLETT PACKARD ENTPR DEV LP4HEWLETT PACKARD DEVELOPMENT CO3COMPAQ INFORMATION TECHNOLOGIE2BROWNELL PAUL V1
Top patents by PatentIndex Score
23 records- 0194US6286083B1Computer system with adaptive memory arbitration schemeCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 4, 2001·213 cites·26 claims
- 0284US6356972B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Mar 12, 2002·34 cites·17 claims
- 0383US6505260B2Computer system with adaptive memory arbitration schemeCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Jan 7, 2003·34 cites·54 claims
- 0483US5905509AAccelerated Graphics Port two level Gart cache having distributed first level cachesCOMPAQ COMPUTER CORP·Filed 1997·Granted May 18, 1999·116 cites·34 claims
- 0576US6275885B1System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cacheCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 14, 2001·71 cites·41 claims
- 0676US6160562ASystem and method for aligning an initial cache line of data read from local memory by an input/output deviceCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 12, 2000·73 cites·18 claims
- 0774US6202101B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 13, 2001·58 cites·10 claims
- 0873US6247102B1Computer system employing memory controller and bridge interface permitting concurrent operationCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 12, 2001·68 cites·41 claims
- 0972US6829665B2Next snoop predictor in a host controllerHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 7, 2004·17 cites·21 claims
- 1072US6272651B1System and method for improving processor read latency in a system employing error checking and correctionCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 7, 2001·61 cites·19 claims
- 1164US10372400B2Video management for compute nodesHEWLETT PACKARD ENTPR DEV LP·Filed 2015·Granted Aug 6, 2019·1 cites·11 claims
- 1264US6279065B1Computer system with improved memory accessCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 21, 2001·43 cites·18 claims
- 1358US8174977B2End-to-end flow control in a networkBROWNELL PAUL V·Filed 2007·Granted May 8, 2012·3 cites·16 claims
- 1455US11138140B2Configuring first subsystem with a master processor and a second subsystem with a slave processorHEWLETT PACKARD ENTPR DEV LP·Filed 2020·Granted Oct 5, 2021·0 cites·18 claims
- 1554US11360782B2Processors to configure subsystems while other processors are held in resetHEWLETT PACKARD ENTPR DEV LP·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 1651US6209052B1System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiterCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 27, 2001·23 cites·18 claims
- 1750US7876759B2Quality of service with control flow packet filteringHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Jan 25, 2011·0 cites·23 claims
- 1848US6961800B2Method for improving processor performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 1, 2005·2 cites·23 claims
- 1947US10404244B2Adjustments of output clocksHEWLETT PACKARD ENTPR DEV LP·Filed 2017·Granted Sep 3, 2019·0 cites·15 claims
- 2045US6249847B1Computer system with synchronous memory arbiter that permits asynchronous memory requestsCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 19, 2001·17 cites·13 claims
- 2143US6199118B1System and method for aligning an initial cache line of data read from an input/output device by a central processing unitCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 6, 2001·15 cites·18 claims
- 2240US6216190B1System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral busCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 10, 2001·12 cites·22 claims
- 2338US2003065860A1Internal control bus in a multiple processor/multiple bus systemFiled 2001·Application pending·0 cites
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