Inventor · disambiguated record
Ibrahim Abdel-Rahman Ouda
Also filed as: OUDA IBRAHIM · OUDA IBRAHIM A · OUDA IBRAHIM ABDEL-RAHMAN
8 granted patents·13 pending applications·31 citations·filing 2003–2022
82Inventor score
Top patents by PatentIndex Score
21 records- 0176US7382777B2Method for implementing actions based on packet classification and lookup resultsIBM·Filed 2003·Granted Jun 3, 2008·22 cites·6 claims
- 0272US11853251B2On-die chip-to-chip (C2C) link state monitorQUALCOMM INC·Filed 2022·Granted Dec 26, 2023·1 cites·16 claims
- 0362US8792332B2Implementing lane shuffle for fault-tolerant communication linksHECKENDORF RYAN ABEL·Filed 2010·Granted Jul 29, 2014·2 cites·14 claims
- 0458US7809008B2Methods and apparatus for routing packetsIBM·Filed 2008·Granted Oct 5, 2010·1 cites·7 claims
- 0558US7539840B2Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2006·Granted May 26, 2009·1 cites·6 claims
- 0653US7362753B2Method and hardware apparatus for implementing frame alteration commandsIBM·Filed 2003·Granted Apr 22, 2008·3 cites·9 claims
- 0753US2009187695A1Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2009·Application pending·0 cites
- 0850US7961732B2Method and hardware apparatus for implementing frame alteration commandsIBM·Filed 2008·Granted Jun 14, 2011·0 cites·9 claims
- 0950US7411956B2Methods and apparatus for routing packetsIBM·Filed 2003·Granted Aug 12, 2008·1 cites·27 claims
- 1050US2008198853A1Apparatus for implementing actions based on packet classification and lookup resultsIBM·Filed 2008·Application pending·0 cites
- 1143US2007180269A1I/O address translation blocking in a secure system during power-on-resetIBM·Filed 2006·Application pending·0 cites
- 1243US2007180158A1Method for command list ordering after multiple cache missesIBM·Filed 2006·Application pending·0 cites
- 1343US2007180157A1Method for cache hit under miss collision handlingIBM·Filed 2006·Application pending·0 cites
- 1443US2007180156A1Method for completing IO commands after an IO translation missIBM·Filed 2006·Application pending·0 cites
- 1542US2005071595A1Methods and apparatus for allocating memoryIBM·Filed 2003·Application pending·0 cites
- 1641US2007006009A1Methods and apparatus for aligning dataIBM·Filed 2005·Application pending·0 cites
- 1740US2008183916A1Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 1840US2008168206A1Methods and Apparatus for Interfacing a Processor and a MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 1932US2013185477A1Variable latency memory delay implementationACUNA VICTOR A·Filed 2012·Application pending·0 cites
- 2031US2013159591A1Verifying data received out-of-order from a busACUNA VICTOR A·Filed 2011·Application pending·0 cites
- 2130US2008168298A1Methods and Apparatus for Calibrating Heterogeneous Memory InterfacesBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →