Inventor · disambiguated record
Bill Nale
Also filed as: NALE BILL · NALE BILL H
64 granted patents·8 pending applications·394 citations·filing 2004–2024
98Inventor score
Top patents by PatentIndex Score
72 records- 0199US11688452B2Refresh command control for host assist of row hammer mitigationINTEL CORP·Filed 2022·Granted Jun 27, 2023·12 cites·20 claims
- 0299US11282561B2Refresh command control for host assist of row hammer mitigationINTEL CORP·Filed 2021·Granted Mar 22, 2022·11 cites·20 claims
- 0397US10950288B2Refresh command control for host assist of row hammer mitigationINTEL CORP·Filed 2019·Granted Mar 16, 2021·19 cites·20 claims
- 0497US10872011B2Internal error checking and correction (ECC) with extra system bitsINTEL CORP·Filed 2017·Granted Dec 22, 2020·27 cites·23 claims
- 0597US10241943B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted Mar 26, 2019·19 cites·17 claims
- 0697US9619408B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2016·Granted Apr 11, 2017·30 cites·9 claims
- 0796US10282323B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2018·Granted May 7, 2019·14 cites·4 claims
- 0896US9342453B2Memory channel that supports near memory and far memory accessNALE BILL·Filed 2011·Granted May 17, 2016·80 cites·16 claims
- 0994US10636476B2Row hammer mitigation with randomization of target row selectionINTEL CORP·Filed 2018·Granted Apr 28, 2020·17 cites·20 claims
- 1094US10496473B2Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)INTEL CORP·Filed 2017·Granted Dec 3, 2019·11 cites·18 claims
- 1194US10282322B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2017·Granted May 7, 2019·14 cites·20 claims
- 1294US10146711B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2016·Granted Dec 4, 2018·14 cites·27 claims
- 1393US7454586B2Memory device commandsINTEL CORP·Filed 2005·Granted Nov 18, 2008·35 cites·19 claims
- 1492US10360096B2Error handling in transactional buffered memoryINTEL CORP·Filed 2017·Granted Jul 23, 2019·12 cites·23 claims
- 1590US10152370B2Method and apparatus for determining a timing adjustment of output to a host memory controllerINTEL CORP·Filed 2015·Granted Dec 11, 2018·5 cites·22 claims
- 1690US9811420B2Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)INTEL CORP·Filed 2015·Granted Nov 7, 2017·7 cites·16 claims
- 1788US9990246B2Memory systemINTEL CORP·Filed 2013·Granted Jun 5, 2018·6 cites·18 claims
- 1887US9658963B2Speculative reads in buffered memoryINTEL CORP·Filed 2014·Granted May 23, 2017·8 cites·20 claims
- 1986US10691626B2Memory channel that supports near memory and far memory accessINTEL CORP·Filed 2019·Granted Jun 23, 2020·2 cites·14 claims
- 2085US10802532B2Techniques to mirror a command/address or interpret command/address logic at a memory deviceINTEL CORP·Filed 2019·Granted Oct 13, 2020·3 cites·22 claims
- 2185US10747605B2Method and apparatus for providing a host memory controller write credits for write commandsINTEL CORP·Filed 2016·Granted Aug 18, 2020·4 cites·25 claims
- 2284US10839887B2Applying chip select for memory device identification and power management controlINTEL CORP·Filed 2017·Granted Nov 17, 2020·3 cites·22 claims
- 2380US9740646B2Early identification in transactional buffered memoryINTEL CORP·Filed 2014·Granted Aug 22, 2017·4 cites·20 claims
- 2479US11699471B2Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidthINTEL CORP·Filed 2020·Granted Jul 11, 2023·1 cites·20 claims
- 2578US11990172B2Refresh command control for host assist of row hammer mitigationINTEL CORP·Filed 2023·Granted May 21, 2024·0 cites·20 claims
- 2677US10884958B2DIMM for a high bandwidth memory channelINTEL CORP·Filed 2018·Granted Jan 5, 2021·2 cites·18 claims
- 2776US10795755B2Method and apparatus for performing error handling operations using error signalsINTEL CORP·Filed 2016·Granted Oct 6, 2020·2 cites·16 claims
- 2876US10579462B2Method and apparatus for using an error signal to indicate a write request error and write request acceptanceINTEL CORP·Filed 2016·Granted Mar 3, 2020·1 cites·20 claims
- 2976US9852021B2Method and apparatus for encoding registers in a memory moduleINTEL CORP·Filed 2015·Granted Dec 26, 2017·3 cites·18 claims
- 3075US10692560B2Periodic calibrations during memory device self refreshINTEL CORP·Filed 2018·Granted Jun 23, 2020·2 cites·16 claims
- 3174US12190979B2Dynamic random access memory built-in self-test power fail mitigationINTEL CORP·Filed 2023·Granted Jan 7, 2025·0 cites·16 claims
- 3274US10061719B2Packed write completionsINTEL CORP·Filed 2014·Granted Aug 28, 2018·5 cites·15 claims
- 3373US10198379B2Early identification in transactional buffered memoryINTEL CORP·Filed 2017·Granted Feb 5, 2019·1 cites·22 claims
- 3472US10997096B2Enumerated per device addressability for memory subsystemsINTEL CORP·Filed 2018·Granted May 4, 2021·1 cites·23 claims
- 3571US10810141B2Memory control management of a processorINTEL CORP·Filed 2017·Granted Oct 20, 2020·1 cites·28 claims
- 3671US10592445B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2018·Granted Mar 17, 2020·2 cites·31 claims
- 3770US11790976B2Periodic calibrations during memory device self refreshINTEL CORP·Filed 2022·Granted Oct 17, 2023·0 cites·5 claims
- 3869US2025077352A1Memory chip with per row activation count having error correction code protectionINTEL CORP·Filed 2024·Application pending·0 cites
- 3968US10339072B2Read delivery for memory subsystem with narrow bandwidth repeater channelINTEL CORP·Filed 2016·Granted Jul 2, 2019·1 cites·26 claims
- 4068US9251874B2Memory interface signal reductionNALE BILL·Filed 2010·Granted Feb 2, 2016·2 cites·15 claims
- 4167US10198306B2Method and apparatus for a memory module to accept a command in multiple partsINTEL CORP·Filed 2015·Granted Feb 5, 2019·1 cites·21 claims
- 4267US9904591B2Device, system and method to restrict access to data error informationINTEL CORP·Filed 2015·Granted Feb 27, 2018·1 cites·25 claims
- 4366US11276453B2Periodic calibrations during memory device self refreshINTEL CORP·Filed 2020·Granted Mar 15, 2022·0 cites·8 claims
- 4465USRE50373EReading from a mode register having different read and write timingSONY GROUP CORP·Filed 2021·Granted Apr 8, 2025·0 cites·31 claims
- 4565US9632862B2Error handling in transactional buffered memoryINTEL CORP·Filed 2014·Granted Apr 25, 2017·1 cites·18 claims
- 4664US7188208B2Side-by-side inverted memory address and command busesINTEL CORP·Filed 2004·Granted Mar 6, 2007·9 cites·20 claims
- 4762US11335395B2Applying chip select for memory device identification and power management controlINTEL CORP·Filed 2020·Granted May 17, 2022·0 cites·19 claims
- 4861US12164373B2Memory chip with per row activation count having error correction code protectionINTEL CORP·Filed 2021·Granted Dec 10, 2024·0 cites·19 claims
- 4961US10185618B2Method and apparatus for selecting one of a plurality of bus interface configurations to useINTEL CORP·Filed 2016·Granted Jan 22, 2019·0 cites·24 claims
- 5060US12443367B2Perfect row hammer tracking with multiple count incrementsINTEL CORP·Filed 2021·Granted Oct 14, 2025·0 cites·20 claims
Showing the top 50 of 72 patent records by PatentIndex Score.
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