Inventor · disambiguated record
Chien-Mo Li
Also filed as: LI CHIEN-MO
7 granted patents·1 pending application·1 citations·filing 2010–2021
70Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD4REALTEK SEMICONDUCTOR CORP2CHANG MING TUNG1UNIV NAT TAIWAN1
Top patents by PatentIndex Score
8 records- 0169US11500018B2Asynchronous circuits and test methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 15, 2022·0 cites·20 claims
- 0266US10429440B2Design-for-test for asynchronous circuit elementsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Oct 1, 2019·1 cites·20 claims
- 0364US11047911B2Asynchronous circuits and test methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 29, 2021·0 cites·20 claims
- 0462US11073552B2Design-for-test for asynchronous circuit elementsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 27, 2021·0 cites·20 claims
- 0546US9983264B2Multiple defect diagnosis method and machine readable mediaREALTEK SEMICONDUCTOR CORP·Filed 2014·Granted May 29, 2018·0 cites·14 claims
- 0640US9213799B2Systematic defect analysis method and machine readable mediaREALTEK SEMICONDUCTOR CORP·Filed 2014·Granted Dec 15, 2015·0 cites·3 claims
- 0733US2010185909A1Asynchronous Scan Chain CircuitUNIV NAT TAIWAN·Filed 2010·Application pending·0 cites
- 0831US8468407B2Method for creating test clock domain during integrated circuit design, and associated computer readable mediumCHANG MING-TUNG·Filed 2011·Granted Jun 18, 2013·0 cites·17 claims
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