Inventor · disambiguated record
Avinash Sodani
Also filed as: SODANI AVINASH
75 granted patents·21 pending applications·332 citations·filing 1997–2024
98Inventor score
Files withMARVELL ASIA PTE LTD37INTEL CORP31CAVIUM LLC7MARVELL ASIA PTE LTD REGISTRATION NO 199702379M4HINTON GLENN J3
Top patents by PatentIndex Score
96 records- 0198US12112174B2Streaming engine for machine learning architectureCAVIUM LLC·Filed 2018·Granted Oct 8, 2024·38 cites·29 claims
- 0298US10896045B2Architecture for dense operations in machine learning inference engineCAVIUM LLC·Filed 2018·Granted Jan 19, 2021·37 cites·25 claims
- 0394US11635739B1System and method to manage power to a desired power profileMARVELL ASIA PTE LTD·Filed 2020·Granted Apr 25, 2023·3 cites·29 claims
- 0494US11340673B1System and method to manage power throttlingMARVELL ASIA PTE LTD·Filed 2020·Granted May 24, 2022·5 cites·25 claims
- 0592US12112175B1Method and apparatus for performing machine learning operations in parallel on machine learning hardwareMARVELL ASIA PTE LTD·Filed 2022·Granted Oct 8, 2024·2 cites·15 claims
- 0692US11016801B1Architecture to support color scheme-based synchronization for machine learningMARVELL ASIA PTE LTD·Filed 2019·Granted May 25, 2021·9 cites·22 claims
- 0791US10275001B2Thermal throttling of electronic devicesINTEL CORP·Filed 2015·Granted Apr 30, 2019·15 cites·16 claims
- 0888US11829492B1System and method for hardware-based register protection mechanismMARVELL ASIA PTE LTD·Filed 2021·Granted Nov 28, 2023·2 cites·30 claims
- 0988US10997510B1Architecture to support tanh and sigmoid operations for inference acceleration in machine learningMARVELL ASIA PTE LTD·Filed 2019·Granted May 4, 2021·6 cites·22 claims
- 1087US2025284499A1Streaming engine for machine learning architectureMARVELL ASIA PTE LTD·Filed 2024·Application pending·0 cites
- 1186US10824433B2Array-based inference engine for machine learningCAVIUM LLC·Filed 2018·Granted Nov 3, 2020·2 cites·19 claims
- 1285US9898351B2Method and apparatus for user-level thread synchronization with a monitor and MWAIT architectureINTEL CORP·Filed 2015·Granted Feb 20, 2018·6 cites·18 claims
- 1384US10929779B1Architecture to support synchronization between core and inference engine for machine learningMARVELL ASIA PTE LTD·Filed 2019·Granted Feb 23, 2021·3 cites·20 claims
- 1484US10891136B1Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instructionMARVELL INT LTD·Filed 2019·Granted Jan 12, 2021·4 cites·17 claims
- 1583US11995448B1Method and apparatus for performing machine learning operations in parallel on machine learning hardwareMARVELL ASIA PTE LTD·Filed 2021·Granted May 28, 2024·1 cites·36 claims
- 1682US7502912B2Method and apparatus for rescheduling operations in a processorINTEL CORP·Filed 2003·Granted Mar 10, 2009·33 cites·24 claims
- 1781US11927932B2System and method to manage power to a desired power profileMARVELL ASIA PTE LTD·Filed 2023·Granted Mar 12, 2024·0 cites·36 claims
- 1881US5845103AComputer with dynamic instruction reuseWISCONSIN ALUMNI RES FOUND·Filed 1997·Granted Dec 1, 1998·98 cites·11 claims
- 1980US7721076B2Tracking an oldest processor event using information stored in a register and queue entryINTEL CORP·Filed 2006·Granted May 18, 2010·10 cites·25 claims
- 2079US11507170B1Power management and current/ramp detection mechanismMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 22, 2022·1 cites·24 claims
- 2177US8438369B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2010·Granted May 7, 2013·4 cites·13 claims
- 2275US11977963B2System and method for INT9 quantizationMARVELL ASIA PTE LTD·Filed 2022·Granted May 7, 2024·0 cites·39 claims
- 2375US7404065B2Flow optimization and prediction for VSSE memory operationsINTEL CORP·Filed 2005·Granted Jul 22, 2008·7 cites·23 claims
- 2473US12169719B1Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engineMARVELL ASIA PTE LTD·Filed 2021·Granted Dec 17, 2024·0 cites·42 claims
- 2573US10102129B2Minimizing snoop traffic locally and across cores on a chip multi-core fabricINTEL CORP·Filed 2015·Granted Oct 16, 2018·3 cites·25 claims
- 2672US11687837B2Architecture to support synchronization between core and inference engine for machine learningMARVELL ASIA PTE LTD·Filed 2022·Granted Jun 27, 2023·0 cites·30 claims
- 2772US2021055934A1Array-based inference engine for machine learningMARVELL ASIA PTE LTD·Filed 2020·Application pending·0 cites
- 2871US11842197B2System and methods for tag-based synchronization of tasks for machine learning operationsMARVELL ASIA PTE LTD·Filed 2023·Granted Dec 12, 2023·0 cites·22 claims
- 2970US8521993B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2007·Granted Aug 27, 2013·4 cites·4 claims
- 3069US11995569B2Architecture to support tanh and sigmoid operations for inference acceleration in machine learningMARVELL ASIA PTE LTD·Filed 2021·Granted May 28, 2024·0 cites·34 claims
- 3169US11687136B2System and method to manage power throttlingMARVELL ASIA PTE LTD·Filed 2022·Granted Jun 27, 2023·0 cites·27 claims
- 3269US10929760B1Architecture for table-based mathematical operations for inference acceleration in machine learningMARVELL ASIA PTE LTD·Filed 2019·Granted Feb 23, 2021·1 cites·19 claims
- 3369US7711898B2Register alias table cache to map a logical register to a physical registerINTEL CORP·Filed 2003·Granted May 4, 2010·14 cites·20 claims
- 3469US2022188108A1System and method for handling floating point hardware exceptionMARVELL ASIA PTE LTD·Filed 2022·Application pending·0 cites
- 3569US2022188111A1System and method for handling floating point hardware exceptionMARVELL ASIA PTE LTD·Filed 2022·Application pending·0 cites
- 3669US2022188109A1System and method for handling floating point hardware exceptionMARVELL ASIA PTE LTD·Filed 2022·Application pending·0 cites
- 3769US2022188110A1System and method for handling floating point hardware exceptionMARVELL ASIA PTE LTD·Filed 2022·Application pending·0 cites
- 3868US11789513B1Power management and current/ramp detection mechanismMARVELL ASIA PTE LTD·Filed 2022·Granted Oct 17, 2023·0 cites·20 claims
- 3968US11403561B2Architecture to support synchronization between core and inference engine for machine learningMARVELL ASIA PTE LTD·Filed 2020·Granted Aug 2, 2022·0 cites·21 claims
- 4068US11256517B2Architecture of crossbar of inference engineCAVIUM LLC·Filed 2018·Granted Feb 22, 2022·0 cites·21 claims
- 4168US11086633B2Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engineCAVIUM LLC·Filed 2018·Granted Aug 10, 2021·0 cites·23 claims
- 4268US9081688B2Obtaining data for redundant multithreading (RMT) executionHINTON GLENN J·Filed 2008·Granted Jul 14, 2015·4 cites·15 claims
- 4367US11734608B2Address interleaving for machine learningMARVELL ASIA PTE LTD·Filed 2020·Granted Aug 22, 2023·0 cites·16 claims
- 4467US11029963B2Architecture for irregular operations in machine learning inference engineCAVIUM LLC·Filed 2018·Granted Jun 8, 2021·0 cites·21 claims
- 4567US10970080B2Systems and methods for programmable hardware architecture for machine learningCAVIUM LLC·Filed 2018·Granted Apr 6, 2021·0 cites·26 claims
- 4666US11494676B2Architecture for table-based mathematical operations for inference acceleration in machine learningMARVELL ASIA PTE LTD·Filed 2020·Granted Nov 8, 2022·0 cites·19 claims
- 4764US11551148B2System and method for INT9 quantizationMARVELL ASIA PTE LTD·Filed 2020·Granted Jan 10, 2023·0 cites·25 claims
- 4864US11301247B2System and method for handling floating point hardware exceptionMARVELL ASIA PTE LTD REGISTRATION NO 199702379M·Filed 2020·Granted Apr 12, 2022·0 cites·36 claims
- 4963US11210105B1Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instructionMARVELL ASIA PTE LTD·Filed 2020·Granted Dec 28, 2021·0 cites·19 claims
- 5063US9524191B2Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elementsMARDEN MORRIS·Filed 2010·Granted Dec 20, 2016·1 cites·12 claims
Showing the top 50 of 96 patent records by PatentIndex Score.
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