Inventor · disambiguated record
Srivathsa Dhruvanarayan
Also filed as: DHRUVANARAYAN SRIVATHSA
18 granted patents·3 pending applications·72 citations·filing 2012–2024
92Inventor score
Top patents by PatentIndex Score
21 records- 0195US10686735B1Packet reconstruction at deparserBAREFOOT NETWORKS INC·Filed 2017·Granted Jun 16, 2020·30 cites·22 claims
- 0294US11321607B2Machine learning network implemented by statically scheduled instructions, with compilerSIMA TECH INC·Filed 2020·Granted May 3, 2022·9 cites·18 claims
- 0392US10757028B1Configurable forwarding element deparserBAREFOOT NETWORKS INC·Filed 2017·Granted Aug 25, 2020·9 cites·21 claims
- 0492US10694006B1Generation of descriptive data for packet fieldsBAREFOOT NETWORKS INC·Filed 2017·Granted Jun 23, 2020·10 cites·16 claims
- 0586US11425058B2Generation of descriptive data for packet fieldsBAREFOOT NETWORKS INC·Filed 2020·Granted Aug 23, 2022·2 cites·21 claims
- 0685US11403519B2Machine learning network implemented by statically scheduled instructions, with system-on-chipSIMA TECH INC·Filed 2020·Granted Aug 2, 2022·2 cites·20 claims
- 0784US11488066B2Efficient convolution of multi-channel input samples with multiple kernelsSIMA TECH INC·Filed 2020·Granted Nov 1, 2022·2 cites·20 claims
- 0880US11474557B2Multichip timing synchronization circuits and methodsGROQ INC·Filed 2020·Granted Oct 18, 2022·1 cites·17 claims
- 0978US11354570B2Machine learning network implemented by statically scheduled instructions, with MLA chipSIMA TECH INC·Filed 2020·Granted Jun 7, 2022·1 cites·16 claims
- 1076US11886981B2Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructionsSIMA TECH INC·Filed 2020·Granted Jan 30, 2024·1 cites·20 claims
- 1174US10824188B2Multichip timing synchronization circuits and methodsGROQ INC·Filed 2019·Granted Nov 3, 2020·1 cites·20 claims
- 1273US12375588B2Generation of descriptive data for packet fieldsBAREFOOT NETWORKS INC·Filed 2022·Granted Jul 29, 2025·0 cites·12 claims
- 1371US10949199B1Copying packet data to mirror bufferBAREFOOT NETWORKS INC·Filed 2017·Granted Mar 16, 2021·1 cites·20 claims
- 1471US8897292B2Low pass filter for hierarchical pipelined distributed scheduling traffic managerERICSSON TELEFON AB L M·Filed 2012·Granted Nov 25, 2014·3 cites·12 claims
- 1571US2023023303A1Machine learning network implemented by statically scheduled instructionsSIMA TECH INC·Filed 2022·Application pending·0 cites
- 1660US2021105220A1Queue scheduler control via packet dataBAREFOOT NETWORKS INC·Filed 2020·Application pending·0 cites
- 1756US10848429B1Queue scheduler control via packet dataBAREFOOT NETWORKS INC·Filed 2017·Granted Nov 24, 2020·0 cites·25 claims
- 1854US2025307007A1Managing current consumption in a machine learning acceleratorSIMA TECH INC·Filed 2024·Application pending·0 cites
- 1952US11631001B2Heterogeneous computing on a system-on-chip, including machine learning inferenceSIMA TECH INC·Filed 2020·Granted Apr 18, 2023·0 cites·19 claims
- 2051US12333351B2Synchronization of processing elements that execute statically scheduled instructions in a machine learning acceleratorSIMA TECH INC·Filed 2020·Granted Jun 17, 2025·0 cites·21 claims
- 2137US11115147B2Multichip fault managementGROQ INC·Filed 2019·Granted Sep 7, 2021·0 cites·15 claims
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