Inventor

HARELAND SCOTT A

US62 patents

⚠️ This page may combine multiple inventors who share the name “HARELAND SCOTT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARELAND SCOTT A

INTEL CORP

Nonplanar device with stress incorporation layer and method of fabrication

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Method of fabricating an ultra-narrow channel semiconductor device

Tri-gate devices and methods of fabrication

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Methods for integrating replacement metal gate structures

Method and apparatus for improving stability of a 6T CMOS SRAM cell

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Tri-gate devices and methods of fabrication

Tri-gate devices and methods of fabrication

Tri-gate transistor device with stress incorporation layer and method of fabrication

Semiconductor device having a laterally modulated gate workfunction and method of fabrication

Semiconductor device having a laterally modulated gate workfunction and method of fabrication

Method of fabricating an ultra-narrow channel semiconductor device

Method and apparatus for improving stability of a 6T CMOS SRAM cell

Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Method of fabricating a robust gate dielectric using a replacement gate flow

Pre-etch implantation damage for the removal of thin film layers

Method for making a semiconductor device having a high-k gate dielectric

Method of fabricating a robust gate dielectric using a replacement gate flow

Method for making a semiconductor device having an ultra-thin high-k gate dielectric

Method of fabricating semiconductor devices with replacement, coaxial gate structure

Method of fabricating multiple nanowires of uniform length from a single catalytic nanoparticle

Method of forming sub-micron-size structures over a substrate

Semiconductor channel on insulator structure

Semiconductor channel on insulator structure

Method and apparatus for improving stability of a 6T CMOS SRAM cell

Atomic layer deposition using photo-enhanced bond reconfiguration

MEDTRONIC INC

Pace pulse detector for an implantable medical device

Detecting and responding to anti-tachyarrhythmia shocks

Enabling and disabling anti-tachyarrhythmia pacing in a concomitant medical device system

Navigation guidance method for complex catheters

Detecting and responding to anti-tachyarrhythmia shocks

Implantable medical device (IMD) sensing modifications responsive to detected pacing pulses

Catheter breach loop feedback fault detection with active and inactive driver system

Closed-loop therapy stimulation response to patient adjustment

Enabling and disabling anti-tachyarrhythmia pacing in a concomitant medical device system

Navigation with arbitrary catheter geometries and method of contact assessment

Navigation guidance method for complex catheters

Noise detection and modulation of closed-loop therapy action

Method of determining target treatment locations

Navigation with arbitrary catheter geometries and method of contact assessment

HARELAND SCOTT A

Fault-tolerant high voltage delivery in an implantable medical device

Tri-gate transistor device with stress incorporation layer and method of fabrication

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Short circuit fault-tolerance in an implantable medical device

MEDTRONIC CRYOCATH LP

Soft balloon device and system