Inventor · disambiguated record
Brian Schieck
Also filed as: SCHIECK BRIAN · SCHIECK BRIAN S
8 granted patents·105 citations·filing 2004–2021
84Inventor score
Top patents by PatentIndex Score
8 records- 0194US8357931B2Flip chip semiconductor die internal signal access system and methodNVIDIA CORP·Filed 2007·Granted Jan 22, 2013·75 cites·20 claims
- 0272US7842948B2Flip chip semiconductor die internal signal access system and methodNVIDIA CORP·Filed 2004·Granted Nov 30, 2010·24 cites·13 claims
- 0370US10032692B2Semiconductor package structureNVIDIA CORP·Filed 2013·Granted Jul 24, 2018·3 cites·12 claims
- 0460US11495568B2IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperaturesNVIDIA CORP·Filed 2021·Granted Nov 8, 2022·0 cites·14 claims
- 0559US9831225B2Low-impedance power delivery for a packaged dieNVIDIA CORP·Filed 2015·Granted Nov 28, 2017·1 cites·18 claims
- 0657US9190396B2Low-impedance power delivery for a packaged dieTEMPLETON DONALD E·Filed 2012·Granted Nov 17, 2015·2 cites·20 claims
- 0749US10943882B1IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperaturesNVIDIA CORP·Filed 2019·Granted Mar 9, 2021·0 cites·7 claims
- 0843US8951814B2Method of fabricating a flip chip semiconductor die with internal signal accessNVIDIA CORP·Filed 2013·Granted Feb 10, 2015·0 cites·17 claims
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