Inventor · disambiguated record
Eric W. Mahurin
Also filed as: MAHURIN ERIC · MAHURIN ERIC W · MAHURIN ERIC WAYNE
49 granted patents·14 pending applications·334 citations·filing 1997–2024
98Inventor score
Top patents by PatentIndex Score
63 records- 0193US9009449B2Reducing power consumption and resource utilization during miss lookaheadCHOU YUAN C·Filed 2011·Granted Apr 14, 2015·23 cites·19 claims
- 0286US10459723B2SIMD instructions for multi-stage cube networksQUALCOMM INC·Filed 2015·Granted Oct 29, 2019·5 cites·26 claims
- 0383US7401310B1Integrated circuit design with cell-based macrosADVANCED MICRO DEVICES INC·Filed 2006·Granted Jul 15, 2008·21 cites·18 claims
- 0481US10625752B2System and method for online functional testing for error-correcting code functionQUALCOMM INC·Filed 2017·Granted Apr 21, 2020·3 cites·22 claims
- 0580US7242219B1Circuit for parity tree structureADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 10, 2007·13 cites·13 claims
- 0679US11372804B2System and method of loading and replication of sub-vector valuesQUALCOMM INC·Filed 2018·Granted Jun 28, 2022·2 cites·23 claims
- 0776US10346133B1System and method of floating point multiply operation processingQUALCOMM INC·Filed 2017·Granted Jul 9, 2019·2 cites·20 claims
- 0875US11586272B2Power control based on performance modification through pulse modulationQUALCOMM INC·Filed 2019·Granted Feb 21, 2023·2 cites·30 claims
- 0974US10860051B2Proactive clock gating system to mitigate supply voltage droopsQUALCOMM INC·Filed 2019·Granted Dec 8, 2020·2 cites·30 claims
- 1073US8918626B2Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructionsCHOU YUAN C·Filed 2011·Granted Dec 23, 2014·3 cites·16 claims
- 1165US9092213B2Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculationWIEDEMEIER JEFF·Filed 2010·Granted Jul 28, 2015·2 cites·19 claims
- 1263US9678758B2Coprocessor for out-of-order loadsQUALCOMM INC·Filed 2014·Granted Jun 13, 2017·1 cites·19 claims
- 1362US12499345B2Simulated low bit-width quantization using bit shifted neural network parametersQUALCOMM INC·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 1462US10656947B2Processor to perform a bit range isolation instructionINTEL CORP·Filed 2018·Granted May 19, 2020·0 cites·13 claims
- 1562US2025131248A1Efficient multiplication approximation for artificial intelligent (ai) enginesQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1661US2025245494A1Codebook compression for vector quantized neural networksQUALCOMM INC·Filed 2024·Application pending·0 cites
- 1760US12373208B1Processor instruction for dynamic floating point exponent extractionQUALCOMM INC·Filed 2024·Granted Jul 29, 2025·0 cites·20 claims
- 1860US12093800B2Hybrid convolution operationQUALCOMM INC·Filed 2021·Granted Sep 17, 2024·0 cites·30 claims
- 1960US10579380B2System-on-chip (SoC) to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·15 claims
- 2060US10579379B2Processor to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·15 claims
- 2160US10372455B2Hand held device to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Aug 6, 2019·0 cites·19 claims
- 2259US6460130B1Detecting full conditions in a queueADVANCED MICRO DEVICES INC·Filed 1999·Granted Oct 1, 2002·34 cites·24 claims
- 2358US9003170B2Bit range isolation instructions, methods, and apparatusLOKTYUKHIN MAXIM·Filed 2009·Granted Apr 7, 2015·1 cites·12 claims
- 2457US7821298B2Multiplexing using product-of-sums and sum-of-productsMAHURIN ERIC·Filed 2008·Granted Oct 26, 2010·2 cites·19 claims
- 2557US6493819B1Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessorADVANCED MICRO DEVICES INC·Filed 1999·Granted Dec 10, 2002·31 cites·20 claims
- 2656US6539470B1Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including sameADVANCED MICRO DEVICES INC·Filed 1999·Granted Mar 25, 2003·29 cites·21 claims
- 2755US2025370928A1Caching of data using a next read index to save power and improve performanceQUALCOMM INC·Filed 2024·Application pending·0 cites
- 2854US11287872B2Multi-thread power limiting via shared limitQUALCOMM INC·Filed 2020·Granted Mar 29, 2022·0 cites·19 claims
- 2952US12438556B2Single instruction multiple data (SIMD) sparse decompression with variable densityQUALCOMM INC·Filed 2023·Granted Oct 7, 2025·0 cites·24 claims
- 3052US6173300B1Method and circuit for determining leading or trailing zero countADVANCED MICRO DEVICES INC·Filed 1998·Granted Jan 9, 2001·25 cites·12 claims
- 3152US6006244ACircuit for shifting or rotating operands of multiple sizeADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 21, 1999·25 cites·13 claims
- 3252US2022309314A1Artificial Intelligence Processor Architecture For Dynamic Scaling Of Neural Network QuantizationQUALCOMM INC·Filed 2021·Application pending·0 cites
- 3352US2025021498A1Area efficient asynchronous first-in-first-out (fifo) buffer for high bandwidth data transfer using event transfer blocksQUALCOMM INC·Filed 2024·Application pending·0 cites
- 3450US10474461B2Instruction-based synchronization of operations including at least one SIMD scatter operationQUALCOMM INC·Filed 2016·Granted Nov 12, 2019·0 cites·26 claims
- 3548US11669747B2Constraining function approximation hardware integrated with fixed-point to floating-point conversionQUALCOMM INC·Filed 2019·Granted Jun 6, 2023·0 cites·15 claims
- 3648US2016026607A1Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, and related circuits, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Application pending·0 cites
- 3747US2022035891A1Reduced result matrixQUALCOMM INC·Filed 2021·Application pending·0 cites
- 3846US6380724B1Method and circuitry for an undisturbed scannable state elementADVANCED MICRO DEVICES INC·Filed 1999·Granted Apr 30, 2002·13 cites·25 claims
- 3946US2025238199A1STORING FLOATING-POINT VALUES ACCORDING TO AN EXTENDED QFLOAT FLOATING-POINT (xqFP) FORMAT IN PROCESSOR DEVICESQUALCOMM INC·Filed 2024·Application pending·0 cites
- 4045US11609764B2Inserting a proxy read instruction in an instruction pipeline in a processorQUALCOMM INC·Filed 2020·Granted Mar 21, 2023·0 cites·30 claims
- 4145US10152101B2Controlling voltage deviations in processing systemsQUALCOMM INC·Filed 2015·Granted Dec 11, 2018·0 cites·30 claims
- 4244US11669273B2Memory access managementQUALCOMM INC·Filed 2021·Granted Jun 6, 2023·0 cites·30 claims
- 4344US10162752B2Data storage at contiguous memory addressesQUALCOMM INC·Filed 2016·Granted Dec 25, 2018·0 cites·30 claims
- 4444US6243805B1Programming paradigm and microprocessor architecture for exact branch targetingADVANCED MICRO DEVICES INC·Filed 1998·Granted Jun 5, 2001·16 cites·21 claims
- 4544US6151616AMethod and circuit for detecting overflow in operand multiplicationADVANCED MICRO DEVICES INC·Filed 1999·Granted Nov 21, 2000·15 cites·20 claims
- 4644US5991786ACircuit and method for shifting or rotating operands of multiple sizeADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 23, 1999·15 cites·25 claims
- 4742US10489155B2Mixed-width SIMD operations using even/odd register pairs for wide data elementsQUALCOMM INC·Filed 2015·Granted Nov 26, 2019·0 cites·12 claims
- 4840US2018081634A1Piecewise polynomial evaluation instructionQUALCOMM INC·Filed 2016·Application pending·0 cites
- 4940US2017371657A1Scatter to gather operationQUALCOMM INC·Filed 2016·Application pending·0 cites
- 5039US6122651AMethod and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directionsADVANCED MICRO DEVICES INC·Filed 1998·Granted Sep 19, 2000·11 cites·14 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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