Inventor · disambiguated record
Richard Burton
Also filed as: BURTON RICHARD · BURTON RICHARD S · BURTON RICHARD SCOTT
47 granted patents·6 pending applications·887 citations·filing 1995–2025
98Inventor score
Files withATOMERA INC36SEMICONDUCTOR COMPONENTS IND LLC8SKYWORKS SOLUTIONS INC7MOTOROLA INC1SEMICONDUCTOR COMPONENTS IND1
Top patents by PatentIndex Score
53 records- 0199US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0299US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 0398US11935940B2Methods for making bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2022·Granted Mar 19, 2024·6 cites·6 claims
- 0498US11923431B2Bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2022·Granted Mar 5, 2024·6 cites·8 claims
- 0598US11869968B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2022·Granted Jan 9, 2024·8 cites·17 claims
- 0698US11664427B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2022·Granted May 30, 2023·7 cites·32 claims
- 0798US11437487B2Bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2020·Granted Sep 6, 2022·8 cites·11 claims
- 0898US11437486B2Methods for making bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2020·Granted Sep 6, 2022·8 cites·11 claims
- 0998US11387325B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2020·Granted Jul 12, 2022·12 cites·35 claims
- 1098US11329154B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted May 10, 2022·14 cites·18 claims
- 1198US11094818B2Method for making a semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted Aug 17, 2021·18 cites·23 claims
- 1298US11075078B1Method for making a semiconductor device including a superlattice within a recessed etchATOMERA INC·Filed 2020·Granted Jul 27, 2021·21 cites·24 claims
- 1398US10879356B2Method for making a semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Dec 29, 2020·21 cites·26 claims
- 1498US10868120B1Method for making a varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Dec 15, 2020·31 cites·25 claims
- 1598US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 1698US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 1798US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 1898US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 1998US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 2098US10840388B1Varactor with hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 17, 2020·33 cites·23 claims
- 2198US10825901B1Semiconductor devices including hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Nov 3, 2020·32 cites·17 claims
- 2298US10825902B1Varactor with hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Nov 3, 2020·30 cites·22 claims
- 2398US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
- 2498US10777451B2Semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Sep 15, 2020·30 cites·27 claims
- 2598US10580867B1FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·22 claims
- 2697US11183565B2Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methodsATOMERA INC·Filed 2019·Granted Nov 23, 2021·15 cites·22 claims
- 2797US10937868B2Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Mar 2, 2021·19 cites·22 claims
- 2897US10937888B2Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlatticesATOMERA INC·Filed 2019·Granted Mar 2, 2021·19 cites·22 claims
- 2997US10879357B1Method for making a semiconductor device having a hyper-abrupt junction region including a superlatticeATOMERA INC·Filed 2019·Granted Dec 29, 2020·19 cites·17 claims
- 3087US12439618B2Bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2023·Granted Oct 7, 2025·0 cites·16 claims
- 3187US2025107139A1Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2024·Application pending·0 cites
- 3286US2024250146A1Methods for making bipolar junction transistors including emitter-base and base-collector superlatticesATOMERA INC·Filed 2024·Application pending·0 cites
- 3385US12199180B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2023·Granted Jan 14, 2025·0 cites·17 claims
- 3482US6531721B1Structure for a heterojunction bipolar transistorSKYWORKS SOLUTIONS INC·Filed 2001·Granted Mar 11, 2003·28 cites·27 claims
- 3581US6596635B1Method for metallization of a semiconductor substrateSKYWORKS SOLUTIONS INC·Filed 2002·Granted Jul 22, 2003·24 cites·23 claims
- 3679US6858522B1Electrical contact for compound semiconductor device and method for forming sameSKYWORKS SOLUTIONS INC·Filed 2000·Granted Feb 22, 2005·27 cites·20 claims
- 3778US7955943B2High voltage sensor device and method thereforSEMICONDUCTOR COMPONENTS IND·Filed 2009·Granted Jun 7, 2011·7 cites·20 claims
- 3878US6573599B1Electrical contact for compound semiconductor device and method for forming sameSKYWORKS SOLUTIONS INC·Filed 2000·Granted Jun 3, 2003·26 cites·10 claims
- 3977US2025338584A1Method for making dmos devices including a superlattice and field plate for drift region diffusionATOMERA INC·Filed 2025·Application pending·0 cites
- 4076US10008457B2Resonance-coupled signaling between IC modulesSEMICONDUCTOR COMPONENTS IND LLC·Filed 2016·Granted Jun 26, 2018·2 cites·8 claims
- 4173US12382689B2Method for making DMOS devices including a superlattice and field plate for drift region diffusionATOMERA INC·Filed 2024·Granted Aug 5, 2025·0 cites·18 claims
- 4271US5667632AMethod of defining a line widthMOTOROLA INC·Filed 1995·Granted Sep 16, 1997·37 cites·23 claims
- 4369US6768140B1Structure and method in an HBT for an emitter ballast resistor with improved characteristicsSKYWORKS SOLUTIONS INC·Filed 2002·Granted Jul 27, 2004·20 cites·21 claims
- 4464US6673687B1Method for fabrication of a heterojunction bipolar transistorSKYWORKS SOLUTIONS INC·Filed 2002·Granted Jan 6, 2004·10 cites·27 claims
- 4564US2025125149A1Method of fabricating semiconductor devices with isolated superlattice structuresATOMERA INC·Filed 2024·Application pending·0 cites
- 4663US6614117B1Method for metallization of a semiconductor substrate and related structureSKYWORKS SOLUTIONS INC·Filed 2002·Granted Sep 2, 2003·9 cites·13 claims
- 4758US2020294993A1Electrostatic discharge (esd) robust transistors and related methodsSEMICONDUCTOR COMPONENTS IND LLC·Filed 2020·Application pending·0 cites
- 4856US11018216B2High voltage capacitor and methodSEMICONDUCTOR COMPONENTS IND LLC·Filed 2019·Granted May 25, 2021·0 cites·19 claims
- 4953US10637468B2Galvanically-isolated signaling between modules with step-up transformerSEMICONDUCTOR COMPONENTS IND LLC·Filed 2017·Granted Apr 28, 2020·0 cites·17 claims
- 5052US9954523B1Receiver for resonance-coupled signalingSEMICONDUCTOR COMPONENTS IND LLC·Filed 2016·Granted Apr 24, 2018·0 cites·19 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
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