Inventor · disambiguated record
David J. Sager
Also filed as: SAGER DAVID · SAGER DAVID J
75 granted patents·5 pending applications·3,303 citations·filing 1988–2017
99Inventor score
Top patents by PatentIndex Score
80 records- 0197US6385715B1Multi-threading for a processor utilizing a replay queueINTEL CORP·Filed 2001·Granted May 7, 2002·152 cites·29 claims
- 0296US6735682B2Apparatus and method for address calculationINTEL CORP·Filed 2002·Granted May 11, 2004·193 cites·21 claims
- 0394US6636976B1Mechanism to control di/dt for a microprocessorINTEL CORP·Filed 2000·Granted Oct 21, 2003·127 cites·19 claims
- 0493US6981129B1Breaking replay dependency loops in a processor using a rescheduled replay queueINTEL CORP·Filed 2000·Granted Dec 27, 2005·87 cites·23 claims
- 0592US7236920B2Mechanism for estimating and controlling di/dt-induced power supply voltage variationsINTEL CORP·Filed 2005·Granted Jun 26, 2007·25 cites·17 claims
- 0692US6792446B2Storing of instructions relating to a stalled threadINTEL CORP·Filed 2002·Granted Sep 14, 2004·60 cites·12 claims
- 0791US6542921B1Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processorINTEL CORP·Filed 1999·Granted Apr 1, 2003·141 cites·33 claims
- 0890US6877086B1Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counterINTEL CORP·Filed 2000·Granted Apr 5, 2005·66 cites·19 claims
- 0988US6785803B1Processor including replay queue to break livelocksINTEL CORP·Filed 2000·Granted Aug 31, 2004·55 cites·20 claims
- 1088US5519841AMulti instruction register mapperDIGITAL EQUIPMENT CORP·Filed 1992·Granted May 21, 1996·134 cites·18 claims
- 1187US9189233B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSASANKA RUCHIRA·Filed 2012·Granted Nov 17, 2015·13 cites·16 claims
- 1287US5197132ARegister mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recoveryDIGITAL EQUIPMENT CORP·Filed 1990·Granted Mar 23, 1993·129 cites·10 claims
- 1386US10725755B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsINTEL CORP·Filed 2017·Granted Jul 28, 2020·4 cites·17 claims
- 1485US6735688B1Processor having replay architecture with fast and slow replay pathsINTEL CORP·Filed 2000·Granted May 11, 2004·41 cites·23 claims
- 1584US6018786ATrace based instruction cachingINTEL CORP·Filed 1997·Granted Jan 25, 2000·107 cites·46 claims
- 1683US6928647B2Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processorINTEL CORP·Filed 2003·Granted Aug 9, 2005·27 cites·12 claims
- 1782US7035785B2Mechanism for estimating and controlling di/dt-induced power supply voltage variationsINTEL CORP·Filed 2001·Granted Apr 25, 2006·27 cites·22 claims
- 1881US9880842B2Using control flow data structures to direct and track instruction executionINTEL CORP·Filed 2013·Granted Jan 30, 2018·7 cites·23 claims
- 1981US6633970B1Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointerINTEL CORP·Filed 1999·Granted Oct 14, 2003·83 cites·44 claims
- 2081US5966544AData speculatable processor having reply architectureINTEL CORP·Filed 1996·Granted Oct 12, 1999·96 cites·13 claims
- 2180US7219349B2Multi-threading techniques for a processor utilizing a replay queueINTEL CORP·Filed 2004·Granted May 15, 2007·20 cites·12 claims
- 2280US6952764B2Stopping replay tornadoesINTEL CORP·Filed 2001·Granted Oct 4, 2005·29 cites·17 claims
- 2380US6925550B2Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detectionINTEL CORP·Filed 2002·Granted Aug 2, 2005·30 cites·23 claims
- 2480US6487675B2Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2001·Granted Nov 26, 2002·21 cites·53 claims
- 2579US9672019B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSAGER DAVID J·Filed 2010·Granted Jun 6, 2017·6 cites·18 claims
- 2679US5283873ANext line prediction apparatus for a pipelined computed systemDIGITAL EQUIPMENT CORP·Filed 1990·Granted Feb 1, 1994·84 cites·7 claims
- 2778US5179673ASubroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipelineDIGITAL EQUIPMENT CORP·Filed 1989·Granted Jan 12, 1993·58 cites·5 claims
- 2877US6163838AComputer processor with a replay systemINTEL CORP·Filed 1998·Granted Dec 19, 2000·74 cites·26 claims
- 2975US6334182B2Scheduling operations using a dependency matrixINTEL CORP·Filed 1998·Granted Dec 25, 2001·69 cites·15 claims
- 3075US5835745AHardware instruction scheduler for short execution unit latenciesFiled 1996·Granted Nov 10, 1998·75 cites·12 claims
- 3174US5421022AApparatus and method for speculatively executing instructions in a computer systemDIGITAL EQUIPMENT CORP·Filed 1993·Granted May 30, 1995·67 cites·21 claims
- 3274US4881165AMethod and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systemsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Nov 14, 1989·56 cites·13 claims
- 3373US6256745B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 2000·Granted Jul 3, 2001·13 cites·21 claims
- 3473US6170038B1Trace based instruction cachingINTEL CORP·Filed 1999·Granted Jan 2, 2001·60 cites·18 claims
- 3573US5717883AMethod and apparatus for parallel execution of computer programs using information providing for reconstruction of a logical sequential programDIGITAL EQUIPMENT CORP·Filed 1995·Granted Feb 10, 1998·68 cites·20 claims
- 3673US5564118APast-history filtered branch predictionDIGITAL EQUIPMENT CORP·Filed 1994·Granted Oct 8, 1996·52 cites·10 claims
- 3773US5003459ACache memory systemDIGITAL EQUIPMENT CORP·Filed 1988·Granted Mar 26, 1991·45 cites·9 claims
- 3872US7987346B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2011·Granted Jul 26, 2011·2 cites·32 claims
- 3972US7454600B2Method and apparatus for assigning thread priority in a processor or the likeINTEL CORP·Filed 2001·Granted Nov 18, 2008·12 cites·12 claims
- 4072US6425055B1Way-predicting cache memoryINTEL CORP·Filed 1999·Granted Jul 23, 2002·59 cites·36 claims
- 4172US6216234B1Processor having execution core sections operating at different clock ratesINTEL CORP·Filed 1998·Granted Apr 10, 2001·49 cites·9 claims
- 4272US5812810AInstruction coding to support parallel execution of programsDIGITAL EQUIPMENT CORP·Filed 1994·Granted Sep 22, 1998·56 cites·14 claims
- 4371US7398372B2Fusing load and alu operationsINTEL CORP·Filed 2002·Granted Jul 8, 2008·15 cites·34 claims
- 4471US4825412ALockout registersDIGITAL EQUIPMENT CORP·Filed 1988·Granted Apr 25, 1989·48 cites·4 claims
- 4570US6880069B1Replay instruction morphingINTEL CORP·Filed 2000·Granted Apr 12, 2005·14 cites·1 claims
- 4670US6094717AComputer processor with a replay system having a plurality of checkersINTEL CORP·Filed 1998·Granted Jul 25, 2000·55 cites·30 claims
- 4770US5619662AMemory reference taggingDIGITAL EQUIPMENT CORP·Filed 1994·Granted Apr 8, 1997·52 cites·16 claims
- 4869US7742910B2Mechanism for estimating and controlling di/dt-induced power supply voltage variationsINTEL CORP·Filed 2007·Granted Jun 22, 2010·3 cites·20 claims
- 4968US7200737B1Processor with a replay system that includes a replay queue for improved throughputINTEL CORP·Filed 1999·Granted Apr 3, 2007·49 cites·26 claims
- 5067US5828868AProcessor having execution core sections operating at different clock ratesINTEL CORP·Filed 1996·Granted Oct 27, 1998·38 cites·4 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
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