Inventor

BAUER TREVOR J

US70 patents

⚠️ This page may combine multiple inventors who share the name “BAUER TREVOR J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAUER TREVOR J

XILINX INC

Formation of columnar application specific circuitry using a columnar programmable device

FPGA lookup table with speed read decoder

Architecture and method for partially reconfiguring an FPGA

Interconnect structure for a programmable logic device

Configurable logic element with ability to evaluate five and six input functions

FPGA repeatable interconnect structure with hierarchical interconnect lines

Lookup tables which double as shift registers

Programmable integrated circuit providing efficient implementations of arithmetic functions

High-speed lookup table circuits and methods for programmable logic devices

Interconnect structure for FPGA with configurable delay locked loop

Configurable logic element with fast feedback paths

FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines

FPGA memory element programmably triggered on both clock edges

Input/output interconnect circuit for FPGAs

Logic block structure optimized for sum generation

Large crossbar switch implemented in FPGA

Large crossbar switch implemented in FPGA

FPGA architecture with wide function multiplexers

Interconnect structure for a programmable logic device

FPGA architecture with deep look-up table RAMs

FPGA architecture with offset interconnect lines

FPGA CLE with two independent carry chains

Programmable power reduction in a clock-distribution circuit

Configurable logic element with ability to evaluate five and six input functions

FPGA interconnect structure with high-speed high fanout capability

Structure and method for loading RAM data within a programmable logic device

Tristatable bidirectional buffer for tristate bus lines

Partial reconfiguration of a programmable logic device using an on-chip processor

Structure for optionally cascading shift registers

Integrated circuit having a programmable input structure with bounce capability

Integrated circuit having a programmable input structure with optional fanout capability

FPGA lookup table with high speed read decorder

FPGA lookup table with dual ended writes for ram and shift register modes

Block RAM with configurable data width and parity for use in a field programmable gate array

FPGA architecture with dual-port deep look-up table RAMS

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes

Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure

Structures and methods for avoiding hold time violations in a programmable logic device

Programmable lookup table with dual input and output terminals in RAM mode

Programmable lookup table with dual input and output terminals in shift register mode

Windowing circuit for aligning data and clock signals

Methods for aligning data and clock signals

Multiplexer for implementing logic functions in a programmable logic device

Circuit for measuring signal delays in synchronous memory elements

Wide logic gate implemented in an FPGA configurable logic element

Configurable logic element with ability to evaluate wide logic functions

Multi-product die configurable as two or more programmable integrated circuits of different logic capacities

FIFO in FPGA having logic elements that include cascadable shift registers

KLEIN MATTHEW H

Clock distribution to facilitate gated clocks