Inventor · disambiguated record
James M. Shehadi
Also filed as: SHEHADI JAMES · SHEHADI JAMES M
7 granted patents·1 pending application·40 citations·filing 2012–2019
82Inventor score
Top patents by PatentIndex Score
8 records- 0186US9009531B2Memory subsystem data bus stress testingINTEL CORP·Filed 2012·Granted Apr 14, 2015·10 cites·27 claims
- 0286US8996934B2Transaction-level testing of memory I/O and memory deviceINTEL CORP·Filed 2012·Granted Mar 31, 2015·10 cites·28 claims
- 0384US9003246B2Functional memory array testing with a transaction-level test engineINTEL CORP·Filed 2012·Granted Apr 7, 2015·9 cites·30 claims
- 0481US9009540B2Memory subsystem command bus stress testingMOZAK CHRISTOPHER P·Filed 2012·Granted Apr 14, 2015·8 cites·30 claims
- 0572US9722663B2Interference testingINTEL CORP·Filed 2014·Granted Aug 1, 2017·3 cites·9 claims
- 0659US10516439B2Interference testingINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·9 claims
- 0737US2019332469A1Address range based in-band memory error-correcting code protection module with syndrome bufferINTEL CORP·Filed 2019·Application pending·0 cites
- 0836US10025732B2Preserving deterministic early valid across a clock domain crossingINTEL CORP·Filed 2016·Granted Jul 17, 2018·0 cites·20 claims
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