Inventor

LI JUNTAO

US567 patents

⚠️ This page may combine multiple inventors who share the name “LI JUNTAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI JUNTAO

IBM

Air gap spacer formation for nano-scale semiconductor devices

Buffer regions for blocking unwanted diffusion in nanosheet transistors

Vertical field-effect transistor with uniform bottom spacer

High density nanosheet diodes

Integrating standard-gate and extended-gate nanosheet transistors on the same substrate

Air gap spacer formation for nano-scale semiconductor devices

Stacked nanosheet field effect transistor device with substrate isolation

Fabrication of a vertical fin field effect transistor having a consistent channel width

Fabrication of vertical field effect transistor structure with strained channels

Closely packed vertical transistors with reduced contact resistance

Vertical transistor having uniform bottom spacers

Vertically stacked nanosheet CMOS transistor

Reduction of multi-threshold voltage patterning damage in nanosheet device structure

Method of forming a nanosheet transistor

Inverse T-shaped contact structures having air gap spacers

Formation of stacked nanosheet semiconductor devices

Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

Nanosheet transistor

Integrating thin and thick gate dielectric nanosheet transistors on same chip

Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths

Forming horizontal bipolar junction transistor compatible with nanosheets

Vertical silicon/silicon-germanium transistors with multiple threshold voltages

Nanosheet transistors having different gate dielectric thicknesses on the same chip

Method and structure for improving vertical transistor

Approach to minimization of strain loss in strained fin field effect transistors

Vertical transport FET devices with uniform bottom spacer

Contact having self-aligned air gap spacers

Multiple finFET formation with epitaxy separation

iFinFET

Vertical FET symmetric and asymmetric source/drain formation

Strained vertical field-effect transistor (FET) and method of forming the same

Stacked nanowire devices

Asymmetric FET

Self-forming embedded diffusion barriers

Method and structure for forming vertical transistors with shared gates and separate gates

Integrated strained stacked nanosheet FET

Electrical fuse and/or resistor structures

Electrical fuse and/or resistor structures

Nanosheet capacitor

Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy

Integrated formation of Si and SiGe fins

Self-aligned vias formed using sacrificial metal caps

Inverse T-shaped contact structures having air gap spacers

Vertical stacked nanosheet CMOS transistors with different work function metals

Vertically stacked nanosheet CMOS transistor

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

Producing strained nanosheet field effect transistors using a phase change material

Vertical transistor with reduced gate length variation

GLOBALFOUNDRIES INC

Nanosheet field-effect transistors including a two-dimensional semiconducting material

Methods of forming gate structures for FinFET devices and the resulting semiconductor products