Inventor · disambiguated record
Harindranath Parameswaran
Also filed as: PARAMESWARAN HARINDRANATH
9 granted patents·50 citations·filing 2007–2013
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0186US9064063B1Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraintsYU HENRY·Filed 2012·Granted Jun 23, 2015·13 cites·31 claims
- 0280US9026958B1Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 5, 2015·6 cites·26 claims
- 0376US8813006B1Accelerated characterization of circuits for within-die process variationsPARAMESWARAN HARINDRANATH·Filed 2008·Granted Aug 19, 2014·13 cites·18 claims
- 0474US8694943B1Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awarenessYU HENRY·Filed 2012·Granted Apr 8, 2014·4 cites·42 claims
- 0569US8555237B1Method and apparatus for design rule violation reporting and visualizationJUNEJA PARDEEP·Filed 2012·Granted Oct 8, 2013·6 cites·20 claims
- 0666US8086983B2Method and system for performing improved timing window analysisSHRIVASTAVA SACHIN·Filed 2008·Granted Dec 27, 2011·5 cites·29 claims
- 0765US8711177B1Generation, display, and manipulation of measurements in computer graphical designsMAJUMDER CHAYAN·Filed 2011·Granted Apr 29, 2014·2 cites·33 claims
- 0852US8612199B2Netlist partitioning for characterizing effect of within-die variationsSHRIVASTAVA SACHIN·Filed 2007·Granted Dec 17, 2013·1 cites·30 claims
- 0941US8839183B2Method and apparatus for derived layers visualization and debuggingCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Sep 16, 2014·0 cites·21 claims
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