Inventor · disambiguated record
Robert L. Maziasz
Also filed as: MAZIASZ ROBERT · MAZIASZ ROBERT L · MAZIASZ ROBERT LEE
18 granted patents·1 pending application·1,566 citations·filing 1995–2014
96Inventor score
Files withMOTOROLA INC9FREESCALE SEMICONDUCTOR INC4MAZIASZ ROBERT L4ROZENFELD VLADIMIR PAVLOVICH1SUNDARESWARAN SAVITHRI1
Top patents by PatentIndex Score
19 records- 0197US6209123B1Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistorsMOTOROLA INC·Filed 1996·Granted Mar 27, 2001·629 cites·17 claims
- 0292US5987086AAutomatic layout standard cell routingMOTOROLA INC·Filed 1996·Granted Nov 16, 1999·213 cites·28 claims
- 0390US5666288AMethod and apparatus for designing an integrated circuitMOTOROLA INC·Filed 1995·Granted Sep 9, 1997·182 cites·40 claims
- 0487US5984510AAutomatic synthesis of standard cell layoutsMOTOROLA INC·Filed 1996·Granted Nov 16, 1999·174 cites·38 claims
- 0585US6006024AMethod of routing an integrated circuitMOTOROLA INC·Filed 1996·Granted Dec 21, 1999·153 cites·10 claims
- 0684US8762898B1Double patterning aware routing without stitchingMAZIASZ ROBERT L·Filed 2013·Granted Jun 24, 2014·4 cites·20 claims
- 0776US8612915B1Reducing leakage in standard cellsSUNDARESWARAN SAVITHRI·Filed 2012·Granted Dec 17, 2013·5 cites·20 claims
- 0874US7721245B2System and method for electromigration tolerant cell synthesisFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 18, 2010·11 cites·20 claims
- 0971US8726218B2Transistor-level layout synthesisMAZIASZ ROBERT L·Filed 2012·Granted May 13, 2014·5 cites·15 claims
- 1069US9928331B2Method and control device for circuit layout migrationROZENFELD VLADIMIR PAVLOVICH·Filed 2014·Granted Mar 27, 2018·4 cites·19 claims
- 1168US9293450B2Synthesis of complex cellsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Mar 22, 2016·2 cites·17 claims
- 1268US8978004B2Cell routability prioritizationMAZIASZ ROBERT L·Filed 2012·Granted Mar 10, 2015·3 cites·20 claims
- 1368US5737236AApparatus and method for the automatic determination of a standard library height within an integrated circuit designMOTOROLA INC·Filed 1996·Granted Apr 7, 1998·56 cites·23 claims
- 1468US5689432AIntegrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the methodMOTOROLA INC·Filed 1995·Granted Nov 18, 1997·56 cites·21 claims
- 1557US7904869B2Method of area compaction for integrated circuit layout designFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 8, 2011·2 cites·14 claims
- 1657US7124385B2Method for automated transistor foldingFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Oct 17, 2006·10 cites·17 claims
- 1750US6075934AMethod for optimizing contact pin placement in an integrated circuitMOTOROLA INC·Filed 1997·Granted Jun 13, 2000·26 cites·20 claims
- 1841US2007143716A1Circuit layout compaction using reshapingMAZIASZ ROBERT L·Filed 2003·Application pending·0 cites
- 1940US5901065AApparatus and method for automatically placing ties and connection elements within an integrated circuitMOTOROLA INC·Filed 1996·Granted May 4, 1999·31 cites·32 claims
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