Inventor · disambiguated record
Sven Peyer
Also filed as: PEYER SVEN · PLEYER SVEN
24 granted patents·1 pending application·354 citations·filing 1998–2020
93Inventor score
Top patents by PatentIndex Score
25 records- 0196US6188401B1Script-based user interface implementation defining components using a text markup languageMICROSOFT CORP·Filed 1998·Granted Feb 13, 2001·326 cites·23 claims
- 0288US10664642B1Constructing via meshes for high performance routing on silicon chipsIBM·Filed 2018·Granted May 26, 2020·5 cites·20 claims
- 0379US8930873B1Creating regional routing blockages in integrated circuit designIBM·Filed 2013·Granted Jan 6, 2015·5 cites·20 claims
- 0475US9536037B2Circuit placement with electro-migration mitigationIBM·Filed 2015·Granted Jan 3, 2017·2 cites·13 claims
- 0575US8938702B1Timing driven routing for noise reduction in integrated circuit designIBM·Filed 2013·Granted Jan 20, 2015·5 cites·20 claims
- 0672US10936773B1Sink-based wire tagging in multi-sink integrated circuit netIBM·Filed 2019·Granted Mar 2, 2021·1 cites·20 claims
- 0772US9384316B2Path-based congestion reduction in integrated circuit routingIBM·Filed 2014·Granted Jul 5, 2016·3 cites·17 claims
- 0871US10146902B2Sharing global route topologies in detailed routingIBM·Filed 2017·Granted Dec 4, 2018·1 cites·8 claims
- 0969US10042970B2Sharing global route topologies in detailed routingIBM·Filed 2016·Granted Aug 7, 2018·1 cites·12 claims
- 1069US9922158B2Use of net-based target congestion ratios in global routingIBM·Filed 2016·Granted Mar 20, 2018·1 cites·13 claims
- 1168US10120970B2Global routing framework of integrated circuit based on localized routing optimizationIBM·Filed 2016·Granted Nov 6, 2018·1 cites·14 claims
- 1268US9471741B1Circuit routing based on total negative slackIBM·Filed 2015·Granted Oct 18, 2016·1 cites·7 claims
- 1365US10616103B2Constructing staging trees in hierarchical circuit designsIBM·Filed 2017·Granted Apr 7, 2020·1 cites·20 claims
- 1464US10452801B2Routing of nets of an integrated circuitIBM·Filed 2015·Granted Oct 22, 2019·1 cites·2 claims
- 1559US10977414B2Constructing via meshes for high performance routing on silicon chipsIBM·Filed 2020·Granted Apr 13, 2021·0 cites·20 claims
- 1656US9245084B2Virtual sub-net based routingIBM·Filed 2014·Granted Jan 26, 2016·0 cites·7 claims
- 1755US9418190B2Virtual sub-net based routingIBM·Filed 2014·Granted Aug 16, 2016·0 cites·13 claims
- 1854US10007751B2Use of net-based target congestion ratios in global routingIBM·Filed 2017·Granted Jun 26, 2018·0 cites·7 claims
- 1952US9483601B2Circuit routing based on total negative slackIBM·Filed 2015·Granted Nov 1, 2016·0 cites·13 claims
- 2051US9679101B2Circuit placement with electro-migration mitigationIBM·Filed 2015·Granted Jun 13, 2017·0 cites·7 claims
- 2147US10606976B2Engineering change order aware global routingIBM·Filed 2017·Granted Mar 31, 2020·0 cites·20 claims
- 2246US10452800B2Routing of nets of an integrated circuitIBM·Filed 2015·Granted Oct 22, 2019·0 cites·4 claims
- 2346US9760669B2Congestion mitigation by wire orderingIBM·Filed 2015·Granted Sep 12, 2017·0 cites·15 claims
- 2446US8949761B2Techniques for routing signal wires in an integrated circuit designIBM·Filed 2012·Granted Feb 3, 2015·0 cites·20 claims
- 2540US2020210545A1Construction of staging trees on fully hierarchical vlsi circuit designsIBM·Filed 2019·Application pending·0 cites
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