Inventor · disambiguated record
Jason D. Hibbeler
Also filed as: HIBBELER JASON · HIBBELER JASON D
68 granted patents·7 pending applications·1,396 citations·filing 2001–2017
99Inventor score
Top patents by PatentIndex Score
75 records- 0199US7308669B2Use of redundant routes to increase the yield and reliability of a VLSI layoutIBM·Filed 2005·Granted Dec 11, 2007·211 cites·40 claims
- 0299US7188322B2Circuit layout methodology using a shape processing applicationIBM·Filed 2005·Granted Mar 6, 2007·192 cites·16 claims
- 0398US7484197B2Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designsIBM·Filed 2006·Granted Jan 27, 2009·297 cites·20 claims
- 0498US7302651B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2004·Granted Nov 27, 2007·209 cites·39 claims
- 0597US7503020B2IC layout optimization to improve yieldIBM·Filed 2006·Granted Mar 10, 2009·110 cites·15 claims
- 0693US8736342B1Changing resonant clock modesIBM·Filed 2012·Granted May 27, 2014·21 cites·23 claims
- 0792US9378329B1Immunity to inline charging damage in circuit designsIBM·Filed 2015·Granted Jun 28, 2016·10 cites·11 claims
- 0892US8704576B1Variable resistance switch for wide bandwidth resonant global clock distributionIBM·Filed 2013·Granted Apr 22, 2014·20 cites·20 claims
- 0988US7093234B2Dynamic CPU usage profiling and function call tracingIBM·Filed 2001·Granted Aug 15, 2006·68 cites·19 claims
- 1085US9054682B2Wide bandwidth resonant global clock distributionIBM·Filed 2013·Granted Jun 9, 2015·7 cites·20 claims
- 1184US9058130B2Tunable sector buffer for wide bandwidth resonant global clock distributionIBM·Filed 2013·Granted Jun 16, 2015·7 cites·31 claims
- 1284US8464189B2Technology migration for integrated circuits with radical design restrictionsALLEN ROBERT J·Filed 2010·Granted Jun 11, 2013·6 cites·15 claims
- 1384US8239790B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2011·Granted Aug 7, 2012·4 cites·20 claims
- 1483US7761821B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2007·Granted Jul 20, 2010·9 cites·24 claims
- 1581US10592627B2Optimizing integrated circuit designs based on interactions between multiple integration design rulesIBM·Filed 2017·Granted Mar 17, 2020·3 cites·7 claims
- 1681US10083272B2Integrated circuit design layout optimizer based on process variation and failure mechanismIBM·Filed 2016·Granted Sep 25, 2018·3 cites·20 claims
- 1780US7454721B2Method, apparatus and computer program product for optimizing an integrated circuit layoutIBM·Filed 2006·Granted Nov 18, 2008·11 cites·12 claims
- 1880US7386815B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2005·Granted Jun 10, 2008·9 cites·17 claims
- 1980US6941528B2Use of a layout-optimization tool to increase the yield and reliability of VLSI designsIBM·Filed 2003·Granted Sep 6, 2005·29 cites·27 claims
- 2079US7882463B2Integrated circuit selective scalingIBM·Filed 2008·Granted Feb 1, 2011·8 cites·20 claims
- 2179US7610565B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2007·Granted Oct 27, 2009·6 cites·15 claims
- 2278US8234594B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameANDERSON BRENT A·Filed 2006·Granted Jul 31, 2012·7 cites·17 claims
- 2378US7290226B2Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristicIBM·Filed 2005·Granted Oct 30, 2007·9 cites·17 claims
- 2477US8405751B2Image sensor pixel structure employing a shared floating diffusionHIBBELER JASON D·Filed 2009·Granted Mar 26, 2013·7 cites·16 claims
- 2576US7669170B2Circuit layout methodology using via shape processIBM·Filed 2007·Granted Feb 23, 2010·6 cites·5 claims
- 2676US7363601B2Integrated circuit selective scalingIBM·Filed 2004·Granted Apr 22, 2008·19 cites·10 claims
- 2774US8230378B2Method for IC wiring yield optimization, including wire widening during and after routingCOHN JOHN M·Filed 2009·Granted Jul 24, 2012·5 cites·15 claims
- 2873US8887118B2Setting switch size and transition pattern in a resonant clock distribution systemIBM·Filed 2013·Granted Nov 11, 2014·2 cites·12 claims
- 2973US8850373B2Setting switch size and transition pattern in a resonant clock distribution systemIBM·Filed 2013·Granted Sep 30, 2014·2 cites·5 claims
- 3073US7257783B2Technology migration for integrated circuits with radical design restrictionsIBM·Filed 2004·Granted Aug 14, 2007·12 cites·9 claims
- 3172US8423328B2Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and meanCOHN JOHN M·Filed 2009·Granted Apr 16, 2013·6 cites·27 claims
- 3271US7062729B2Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimizationIBM·Filed 2004·Granted Jun 13, 2006·16 cites·17 claims
- 3370US7260790B2Integrated circuit yield enhancement using Voronoi diagramsIBM·Filed 2004·Granted Aug 21, 2007·15 cites·33 claims
- 3469US7735042B2Context aware sub-circuit layout modificationIBM·Filed 2007·Granted Jun 8, 2010·4 cites·20 claims
- 3566US8429576B2Methods and system for analysis and management of parametric yieldCULP JAMES A·Filed 2012·Granted Apr 23, 2013·1 cites·20 claims
- 3665US8042070B2Methods and system for analysis and management of parametric yieldIBM·Filed 2007·Granted Oct 18, 2011·3 cites·20 claims
- 3765US7984394B2Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2007·Granted Jul 19, 2011·3 cites·4 claims
- 3865US7865848B2Layout optimization using parameterized cellsIBM·Filed 2007·Granted Jan 4, 2011·3 cites·2 claims
- 3965US7487476B2Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis toolIBM·Filed 2006·Granted Feb 3, 2009·2 cites·4 claims
- 4064US7960836B2Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the sameIBM·Filed 2008·Granted Jun 14, 2011·2 cites·20 claims
- 4164US7818694B2IC layout optimization to improve yieldIBM·Filed 2008·Granted Oct 19, 2010·2 cites·20 claims
- 4264US7568173B2Independent migration of hierarchical designs with methods of finding and fixing opens during migrationIBM·Filed 2007·Granted Jul 28, 2009·3 cites·12 claims
- 4364US7490308B2Method for implementing overlay-based modification of VLSI design layoutIBM·Filed 2006·Granted Feb 10, 2009·4 cites·6 claims
- 4463US8010916B2Test yield estimate for semiconductor products created from a libraryIBM·Filed 2008·Granted Aug 30, 2011·2 cites·13 claims
- 4562US9268886B2Setting switch size and transition pattern in a resonant clock distribution systemIBM·Filed 2013·Granted Feb 23, 2016·1 cites·12 claims
- 4662US7389480B2Content based yield prediction of VLSI designsIBM·Filed 2005·Granted Jun 17, 2008·2 cites·6 claims
- 4760US7657859B2Method for IC wiring yield optimization, including wire widening during and after routingIBM·Filed 2005·Granted Feb 2, 2010·1 cites·19 claims
- 4859US7818692B2Automated optimization of device structure during circuit design stageIBM·Filed 2007·Granted Oct 19, 2010·1 cites·10 claims
- 4959US7725864B2Systematic yield in semiconductor manufactureIBM·Filed 2007·Granted May 25, 2010·1 cites·16 claims
- 5059US7721240B2Systematic yield in semiconductor manufactureIBM·Filed 2007·Granted May 18, 2010·1 cites·15 claims
Showing the top 50 of 75 patent records by PatentIndex Score.
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