Inventor · disambiguated record
Erik R. Altman
Also filed as: ALTMAN ERIK · ALTMAN ERIK R · ALTMAN ERIK RICHTER
32 granted patents·10 pending applications·601 citations·filing 1999–2023
97Inventor score
Top patents by PatentIndex Score
42 records- 0196US10078571B2Rule-based adaptive monitoring of application performanceIBM·Filed 2015·Granted Sep 18, 2018·31 cites·14 claims
- 0296US6349361B1Methods and apparatus for reordering and renaming memory references in a multiprocessor computer systemIBM·Filed 2000·Granted Feb 19, 2002·199 cites·25 claims
- 0395US7496733B2System and method of execution of register pointer instructions ahead of instruction issuesIBM·Filed 2007·Granted Feb 24, 2009·38 cites·20 claims
- 0494US6779049B2Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanismIBM·Filed 2000·Granted Aug 17, 2004·74 cites·14 claims
- 0588US9823994B2Dynamically identifying performance anti-patternsIBM·Filed 2015·Granted Nov 21, 2017·6 cites·20 claims
- 0687US10176022B2Dynamically adapting a test workload to accelerate the identification of performance issuesIBM·Filed 2015·Granted Jan 8, 2019·6 cites·17 claims
- 0786US8589662B2Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signalsALTMAN ERIK R·Filed 2012·Granted Nov 19, 2013·10 cites·20 claims
- 0885US8627317B2Automatic identification of bottlenecks using rule-based expert knowledgeALTMAN ERIK R·Filed 2010·Granted Jan 7, 2014·11 cites·25 claims
- 0983US7496494B2Method and system for multiprocessor emulation on a multiprocessor host systemIBM·Filed 2002·Granted Feb 24, 2009·31 cites·2 claims
- 1081US7735072B1Method and apparatus for profiling computer program executionIBM·Filed 2000·Granted Jun 8, 2010·34 cites·35 claims
- 1179US8151092B2Control signal memoization in a multiple instruction issue microprocessorALTMAN ERIK RICHTER·Filed 2005·Granted Apr 3, 2012·10 cites·6 claims
- 1278US6970982B2Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructionsIBM·Filed 2003·Granted Nov 29, 2005·20 cites·12 claims
- 1376US7509457B2Non-homogeneous multi-processor system with shared memoryIBM·Filed 2005·Granted Mar 24, 2009·4 cites·1 claims
- 1474US7461209B2Transient cache storage with discard function for disposable dataIBM·Filed 2005·Granted Dec 2, 2008·6 cites·15 claims
- 1573US7487330B2Method and apparatus for transferring control in a computer system with dynamic compilation capabilityIBM·Filed 2001·Granted Feb 3, 2009·19 cites·15 claims
- 1671US7516310B2Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processorIBM·Filed 2006·Granted Apr 7, 2009·5 cites·3 claims
- 1770US8719548B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessorALTMAN ERIK RICHTER·Filed 2011·Granted May 6, 2014·3 cites·10 claims
- 1870US6907477B2Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processorsIBM·Filed 2004·Granted Jun 14, 2005·11 cites·11 claims
- 1969US7356673B2System and method including distributed instruction buffers for storing frequently executed instructions in predecoded formIBM·Filed 2001·Granted Apr 8, 2008·14 cites·17 claims
- 2067US7953588B2Method and system for efficient emulation of multiprocessor address translation on a multiprocessor hostIBM·Filed 2002·Granted May 31, 2011·11 cites·31 claims
- 2165US7401209B2Limiting entries searched in load reorder queue to between two pointers for match with executing load instructionIBM·Filed 2006·Granted Jul 15, 2008·2 cites·1 claims
- 2264US7865699B2Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2007·Granted Jan 4, 2011·2 cites·25 claims
- 2361US7966478B2Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointersIBM·Filed 2008·Granted Jun 21, 2011·1 cites·1 claims
- 2461US6381691B1Method and apparatus for reordering memory operations along multiple execution paths in a processorIBM·Filed 1999·Granted Apr 30, 2002·37 cites·28 claims
- 2560US7844446B2Method and system for multiprocessor emulation on a multiprocessor host systemIBM·Filed 2009·Granted Nov 30, 2010·1 cites·17 claims
- 2659US7340588B2Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing codeIBM·Filed 2003·Granted Mar 4, 2008·5 cites·39 claims
- 2757US7325124B2System and method of execution of register pointer instructions ahead of instruction issueIBM·Filed 2004·Granted Jan 29, 2008·4 cites·21 claims
- 2855US7971033B2Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence classIBM·Filed 2008·Granted Jun 28, 2011·0 cites·1 claims
- 2954US10346283B2Dynamically identifying performance anti-patternsIBM·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 3054US7206923B2Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-fillingIBM·Filed 2003·Granted Apr 17, 2007·3 cites·22 claims
- 3154US2025004868A1Detection of anomalous system behaviorIBM·Filed 2023·Application pending·0 cites
- 3253US7979682B2Method and system for preventing livelock due to competing updates of prediction informationIBM·Filed 2008·Granted Jul 12, 2011·0 cites·19 claims
- 3353US6704855B1Method and apparatus for reducing encoding needs and ports to shared resources in a processorIBM·Filed 2000·Granted Mar 9, 2004·3 cites·29 claims
- 3450US2024012731A1Detecting exceptional activity during data stream generationIBM·Filed 2022·Application pending·0 cites
- 3549US2007277025A1Method and system for preventing livelock due to competing updates of prediction informationIBM·Filed 2006·Application pending·0 cites
- 3645US2008010440A1Means for supporting and tracking a large number of in-flight stores in an out-of-order processorIBM·Filed 2006·Application pending·0 cites
- 3745US2008010441A1Means for supporting and tracking a large number of in-flight loads in an out-of-order processorIBM·Filed 2006·Application pending·0 cites
- 3844US2007162895A1Mechanism and method for two level adaptive trace predictionIBM·Filed 2006·Application pending·0 cites
- 3944US2008162877A1Non-Homogeneous Multi-Processor System With Shared MemoryALTMAN ERIK RICHTER·Filed 2008·Application pending·0 cites
- 4043US2006174089A1Method and apparatus for embedding wide instruction words in a fixed-length instruction set architectureIBM·Filed 2005·Application pending·0 cites
- 4143US2006190700A1Handling permanent and transient errors using a SIMD unitIBM·Filed 2005·Application pending·0 cites
- 4237US2002112193A1Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profileIBM·Filed 2001·Application pending·0 cites
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