Inventor · disambiguated record
Roberto Passerone
Also filed as: PASSERONE ROBERTO
6 granted patents·126 citations·filing 1999–2011
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
6 records- 0194US7624364B2Data path and placement optimization in an integrated circuit through use of sequential timing informationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 24, 2009·49 cites·4 claims
- 0292US7743354B2Optimizing integrated circuit design through use of sequential timing informationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 22, 2010·36 cites·33 claims
- 0385US8307316B2Reducing critical cycle delay in an integrated circuit design through use of sequential slackALBRECHT CHRISTOPH·Filed 2011·Granted Nov 6, 2012·10 cites·38 claims
- 0479US7913210B2Reducing critical cycle delay in an integrated circuit design through use of sequential slackCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 22, 2011·9 cites·21 claims
- 0578US8589845B2Optimizing integrated circuit design through use of sequential timing informationALBRECHT CHRISTOPH·Filed 2009·Granted Nov 19, 2013·9 cites·14 claims
- 0639US7136947B1System and method for automatically synthesizing interfaces between incompatible protocolsCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Nov 14, 2006·13 cites·39 claims
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