Inventor · disambiguated record
Gobi R. Padmanabhan
Also filed as: PADMANABHAN GOBI · PADMANABHAN GOBI R · PADMANABHAN GOBI RAMAKRISHNAN
40 granted patents·1 pending application·1,187 citations·filing 1993–2010
98Inventor score
Top patents by PatentIndex Score
41 records- 0198US6949421B1Method of forming a vertical MOS transistorNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 27, 2005·240 cites·19 claims
- 0291US7075133B1Semiconductor die with heat and electrical pipesNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jul 11, 2006·57 cites·14 claims
- 0391US5917207AProgrammable polysilicon gate array base cell architectureLSI LOGIC CORP·Filed 1997·Granted Jun 29, 1999·135 cites·20 claims
- 0489US5721151AMethod of fabricating a gate array integrated circuit including interconnectable macro-arraysLSI LOGIC CORP·Filed 1995·Granted Feb 24, 1998·86 cites·13 claims
- 0588US5731223AArray of solder pads on an integrated circuitLSI LOGIC CORP·Filed 1996·Granted Mar 24, 1998·100 cites·6 claims
- 0685US7633131B1MEMS semiconductor sensor deviceNAT SEMICONDUCTOR CORP·Filed 2007·Granted Dec 15, 2009·9 cites·19 claims
- 0784US6781239B1Integrated circuit and method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chipNAT SEMICONDUCTOR CORP·Filed 2001·Granted Aug 24, 2004·21 cites·20 claims
- 0882US6677235B1Silicon die with metal feed through structureNAT SEMICONDUCTOR CORP·Filed 2001·Granted Jan 13, 2004·29 cites·20 claims
- 0980US5777383ASemiconductor chip package with interconnect layers and routing and testing methodsLSI LOGIC CORP·Filed 1996·Granted Jul 7, 1998·70 cites·10 claims
- 1079US7192819B1Semiconductor sensor device using MEMS technologyNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 20, 2007·21 cites·20 claims
- 1179US6833781B1High Q inductor in multi-level interconnectNAT SEMICONDUCTOR CORP·Filed 2002·Granted Dec 21, 2004·27 cites·20 claims
- 1274US5776831AMethod of forming a high electromigration resistant metallization systemLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·36 cites·18 claims
- 1372US7338840B1Method of forming a semiconductor die with heat and electrical pipesNAT SEMICONDUCTOR CORP·Filed 2006·Granted Mar 4, 2008·4 cites·17 claims
- 1472US5585286AImplantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS deviceLSI LOGIC CORP·Filed 1995·Granted Dec 17, 1996·39 cites·16 claims
- 1571US7329555B1Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication processNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 12, 2008·13 cites·14 claims
- 1669US7044908B1Method and system for dynamically adjusting field of view in a capsule endoscopeNAT SEMICONDUCTOR CORP·Filed 2003·Granted May 16, 2006·52 cites·21 claims
- 1768US7052977B1Method of dicing a semiconductor wafer that substantially reduces the width of the saw streetNAT SEMICONDUCTOR CORP·Filed 2004·Granted May 30, 2006·11 cites·19 claims
- 1868US5621616AHigh density CMOS integrated circuit with heat transfer structure for improved coolingLSI LOGIC CORP·Filed 1995·Granted Apr 15, 1997·37 cites·20 claims
- 1967US6946321B1Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chipNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 20, 2005·8 cites·17 claims
- 2065US7399274B1Sensor configuration for a capsule endoscopeNAT SEMICONDUCTOR CORP·Filed 2003·Granted Jul 15, 2008·9 cites·20 claims
- 2159US7790602B1Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnectNAT SEMICONDUCTOR CORP·Filed 2006·Granted Sep 7, 2010·1 cites·17 claims
- 2259US6730969B1Radiation hardened MOS transistorNAT SEMICONDUCTOR CORP·Filed 2002·Granted May 4, 2004·9 cites·21 claims
- 2358US7482228B1Method of forming a MOS transistor with a litho-less gateNAT SEMICONDUCTOR CORP·Filed 2005·Granted Jan 27, 2009·1 cites·19 claims
- 2458US7042092B1Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnectNAT SEMICONDUCTOR CORP·Filed 2001·Granted May 9, 2006·7 cites·23 claims
- 2557US6777288B1Vertical MOS transistorNAT SEMICONDUCTOR CORP·Filed 2002·Granted Aug 17, 2004·6 cites·15 claims
- 2657US5799080ASemiconductor chip having identification/encryption codeLSI LOGIC CORP·Filed 1995·Granted Aug 25, 1998·41 cites·11 claims
- 2757US5600182ABarrier metal technology for tungsten plug interconnectionLSI LOGIC CORP·Filed 1995·Granted Feb 4, 1997·20 cites·26 claims
- 2855US5827777AMethod of making a barrier metal technology for tungsten plug interconnectionLSI LOGIC CORP·Filed 1996·Granted Oct 27, 1998·18 cites·28 claims
- 2954US5358886AMethod of making integrated circuit structure with programmable conductive electrode/interconnect materialLSI LOGIC CORP·Filed 1993·Granted Oct 25, 1994·24 cites·19 claims
- 3050US2010288346A1Configurations and methods to manufacture solar cell device with larger capture cross section and higher optical utilization efficiencyPADMANABHAN GOBI RAMAKRISHNAN·Filed 2010·Application pending·0 cites
- 3149US8288834B1Semiconductor wafer and die that include an integrated circuit and two or more different MEMS-based semiconductor devicesPADMANABHAN GOBI R·Filed 2007·Granted Oct 16, 2012·0 cites·15 claims
- 3249US5702957AMethod of making buried metallization structureLSI LOGIC CORP·Filed 1996·Granted Dec 30, 1997·15 cites·16 claims
- 3345US6746956B1Hermetic seal for silicon die with metal feed through structureNAT SEMICONDUCTOR CORP·Filed 2002·Granted Jun 8, 2004·1 cites·14 claims
- 3445US5874754AMicroelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gatesLSI LOGIC CORP·Filed 1995·Granted Feb 23, 1999·11 cites·26 claims
- 3544US5691218AMethod of fabricating a programmable polysilicon gate array base cell structureLSI LOGIC CORP·Filed 1996·Granted Nov 25, 1997·11 cites·8 claims
- 3641US5717238ASubstrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS deviceLSI LOGIC CORP·Filed 1996·Granted Feb 10, 1998·8 cites·16 claims
- 3740US7109571B1Method of forming a hermetic seal for silicon die with metal feed through structureNAT SEMICONDUCTOR CORP·Filed 2004·Granted Sep 19, 2006·0 cites·18 claims
- 3838US6723593B1Deep submicron MOS transistor with increased threshold voltageNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 20, 2004·0 cites·20 claims
- 3938US5440154ANon-rectangular MOS device configurations for gate array type integrated circuitsLSI LOGIC CORP·Filed 1993·Granted Aug 8, 1995·6 cites·14 claims
- 4037US7230301B1Single-crystal silicon semiconductor structureNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 12, 2007·0 cites·27 claims
- 4135US5796130ANon-rectangular MOS device configurations for gate array type integrated circuitsLSI LOGIC CORP·Filed 1995·Granted Aug 18, 1998·4 cites·10 claims
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