Inventor · disambiguated record
Nicholas Anthony Lanzillo
Also filed as: LANZILLO NICHOLAS A · LANZILLO NICHOLAS ANTHONY
102 granted patents·141 pending applications·124 citations·filing 2017–2024
99Inventor score
Top patents by PatentIndex Score
243 records- 0198US10319629B1Skip via for metal interconnectsIBM·Filed 2018·Granted Jun 11, 2019·25 cites·20 claims
- 0298US10243020B1Structures and methods for embedded magnetic random access memory (MRAM) fabricationIBM·Filed 2017·Granted Mar 26, 2019·18 cites·13 claims
- 0397US11756887B2Backside floating metal for increased capacitanceIBM·Filed 2021·Granted Sep 12, 2023·5 cites·22 claims
- 0497US11152257B2Barrier-less prefilled via formationIBM·Filed 2020·Granted Oct 19, 2021·5 cites·18 claims
- 0595US11894265B2Top via with damascene line and viaIBM·Filed 2021·Granted Feb 6, 2024·2 cites·19 claims
- 0694US11276639B2Conductive lines with subtractive cutsIBM·Filed 2020·Granted Mar 15, 2022·3 cites·18 claims
- 0794US11195795B1Well-controlled edge-to-edge spacing between adjacent interconnectsIBM·Filed 2020·Granted Dec 7, 2021·3 cites·20 claims
- 0893US12148682B2Memory cell in wafer backsideIBM·Filed 2021·Granted Nov 19, 2024·2 cites·7 claims
- 0993US11908791B2Partial subtractive supervia enabling hyper-scalingIBM·Filed 2021·Granted Feb 20, 2024·2 cites·17 claims
- 1093US9985199B1Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shieldIBM·Filed 2017·Granted May 29, 2018·8 cites·13 claims
- 1191US10746782B2Accelerated wafer testing using non-destructive and localized stressIBM·Filed 2017·Granted Aug 18, 2020·4 cites·16 claims
- 1289US12424549B2Skip-level TSV with hybrid dielectric scheme for backside power deliveryIBM·Filed 2022·Granted Sep 23, 2025·1 cites·15 claims
- 1389US11189568B2Top via interconnect having a line with a reduced bottom dimensionIBM·Filed 2020·Granted Nov 30, 2021·2 cites·4 claims
- 1489US11171084B2Top via with next level line selective growthIBM·Filed 2020·Granted Nov 9, 2021·2 cites·14 claims
- 1588US11195792B2Top via stackIBM·Filed 2020·Granted Dec 7, 2021·2 cites·20 claims
- 1688US10553789B1Fully aligned semiconductor device with a skip-level viaIBM·Filed 2018·Granted Feb 4, 2020·4 cites·20 claims
- 1788US10256191B2Hybrid dielectric scheme for varying liner thickness and manganese concentrationIBM·Filed 2017·Granted Apr 9, 2019·4 cites·5 claims
- 1887US11195993B2Encapsulation topography-assisted self-aligned MRAM top contactIBM·Filed 2019·Granted Dec 7, 2021·7 cites·25 claims
- 1985US9941211B1Reducing metallic interconnect resistivity through application of mechanical strainIBM·Filed 2017·Granted Apr 10, 2018·3 cites·14 claims
- 2084US10739397B2Accelerated wafer testing using non-destructive and localized stressIBM·Filed 2017·Granted Aug 11, 2020·2 cites·20 claims
- 2183US11223655B2Semiconductor tool matching and manufacturing management in a blockchainIBM·Filed 2018·Granted Jan 11, 2022·4 cites·20 claims
- 2282US11682617B2High aspect ratio vias for integrated circuitsIBM·Filed 2020·Granted Jun 20, 2023·1 cites·20 claims
- 2381US11289371B2Top vias with selectively retained etch stopsIBM·Filed 2020·Granted Mar 29, 2022·1 cites·20 claims
- 2481US10796833B2Magnetic tunnel junction with low series resistanceIBM·Filed 2018·Granted Oct 6, 2020·2 cites·18 claims
- 2581US10727124B2Structure and method for forming fully-aligned trench with an up-via integration schemeIBM·Filed 2018·Granted Jul 28, 2020·3 cites·20 claims
- 2680US10741751B2Fully aligned semiconductor device with a skip-level viaIBM·Filed 2019·Granted Aug 11, 2020·1 cites·20 claims
- 2779US10770511B2Structures and methods for embedded magnetic random access memory (MRAM) fabricationIBM·Filed 2019·Granted Sep 8, 2020·3 cites·20 claims
- 2878US11139201B2Top via with hybrid metallizationIBM·Filed 2019·Granted Oct 5, 2021·2 cites·19 claims
- 2978US10720567B2Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shieldIBM·Filed 2018·Granted Jul 21, 2020·1 cites·19 claims
- 3077US10978343B2Interconnect structure having fully aligned viasIBM·Filed 2019·Granted Apr 13, 2021·2 cites·25 claims
- 3173US12243819B2Single-mask alternating line depositionIBM·Filed 2022·Granted Mar 4, 2025·0 cites·16 claims
- 3272US11791258B2Conductive lines with subtractive cutsIBM·Filed 2022·Granted Oct 17, 2023·0 cites·20 claims
- 3371US11670542B2Stepped top via for via resistance reductionIBM·Filed 2022·Granted Jun 6, 2023·0 cites·7 claims
- 3470US11854884B2Fully aligned top viasIBM·Filed 2021·Granted Dec 26, 2023·0 cites·20 claims
- 3570US11823998B2Top via with next level line selective growthIBM·Filed 2021·Granted Nov 21, 2023·0 cites·9 claims
- 3670US2023361038A1Topological semi-metal interconnectsIBM·Filed 2023·Application pending·0 cites
- 3769US12506080B2Reduced capacitance between power via bar and gatesIBM·Filed 2022·Granted Dec 23, 2025·0 cites·24 claims
- 3869US12500144B2Backside self aligned skip viaIBM·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 3969US12417979B2Pass-through wiring in notched interconnectIBM·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 4069US11990410B2Top via interconnect having a line with a reduced bottom dimensionIBM·Filed 2021·Granted May 21, 2024·0 cites·20 claims
- 4169US11621189B2Barrier-less prefilled via formationIBM·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 4269US11600565B2Top via stackIBM·Filed 2021·Granted Mar 7, 2023·0 cites·20 claims
- 4369US2025301785A1Cross-couple connect in stacked field effect transistor semiconductorsIBM·Filed 2024·Application pending·0 cites
- 4468US12400960B2Vertical-transport field-effect transistor with backside gate contactIBM·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 4567US11749602B2Topological semi-metal interconnectsIBM·Filed 2020·Granted Sep 5, 2023·0 cites·9 claims
- 4667US11735475B2Removal of barrier and liner layers from a bottom of a viaIBM·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 4766US12417974B2Decoupling capacitance in backside interconnectIBM·Filed 2022·Granted Sep 16, 2025·0 cites·20 claims
- 4866US11232977B2Stepped top via for via resistance reductionIBM·Filed 2020·Granted Jan 25, 2022·0 cites·17 claims
- 4966US11177166B2Etch stop layer removal for capacitance reduction in damascene top via integrationIBM·Filed 2020·Granted Nov 16, 2021·0 cites·17 claims
- 5065US12463132B2Semiconductor structure with backside metallization layersIBM·Filed 2022·Granted Nov 4, 2025·0 cites·20 claims
Showing the top 50 of 243 patent records by PatentIndex Score.
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