Inventor

BRIGGS BENJAMIN D

US170 patents

⚠️ This page may combine multiple inventors who share the name “BRIGGS BENJAMIN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRIGGS BENJAMIN D

IBM

Self-forming barrier for use in air gap formation

Method for maximizing air gap in back end of the line interconnect through via landing modification

Semiconductor device with selective dielectric deposition

Fully aligned via employing selective metal deposition

Reduced tip-to-tip and via pitch at line end

Fully aligned via with integrated air gaps

Skip-vias bypassing a metallization level at minimum pitch

Selective and non-selective barrier layer wet removal

Airgap protection layer for via alignment

Encapsulation topography-assisted self-aligned MRAM top contact

Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material

Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface

Wraparound top electrode line for crossbar array resistive switching device

Sentiment analysis of mental health disorder symptoms

Enabling low resistance gates and contacts integrated with bilayer dielectrics

Semiconductor device formed by wet etch removal of Ru selective to other metals

Skip-vias bypassing a metallization level at minimum pitch

Reduced tip-to-tip and via pitch at line end

Social media modification of behavior and mobile screening for impairment

Selective and non-selective barrier layer wet removal

Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield

Fold over emitter and collector field emission transistor

Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects

Health monitoring using parallel cognitive processing

Forming deep airgaps without flop over

Selective and non-selective barrier layer wet removal

Heterogeneous metallization using solid diffusion removal of metal interconnects

Smartwatch blackbox

Hybrid metal interconnects with a bamboo grain microstructure

Uniform dielectric recess depth during fin reveal

Self aligned via and pillar cut for at least a self aligned double pitch

Fold over emitter and collector field emission transistor

Structure and fabrication method for electromigration immortal nanoscale interconnects

Security key system

Forming chamferless vias using thermally decomposable porefiller

Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones

Increasing cost benefit and energy efficiency with modular delivery drones in inclement weather

Selective CVD alignment-mark topography assist for non-volatile memory

Dynamic rigidity mechanism

Semiconductor device with selective insulator for improved capacitance

Accelerated wafer testing using non-destructive and localized stress

Accelerated wafer testing using non-destructive and localized stress

Structure and method for forming fully-aligned trench with an up-via integration scheme

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Selective ILD deposition for fully aligned via with airgap

Selective recessing to form a fully aligned via

TESSERA LLC

Self-forming barrier for use in air gap formation

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

APPLIED MATERIALS INC

Structure and method of advanced LCoS back-plane having robust pixel via metallization

Method for LCoS DBR multilayer stack protection via sacrificial hardmask for RIE and CMP processes

TESSERA INC

Self-forming barrier for use in air gap formation