Inventor · disambiguated record
Yan Chong
Also filed as: CHONG YAN · CHONG YAN TAT
90 granted patents·1,453 citations·filing 2001–2019
99Inventor score
Top patents by PatentIndex Score
90 records- 0198US6686769B1Programmable I/O element circuit for high speed logic devicesALTERA CORP·Filed 2001·Granted Feb 3, 2004·146 cites·29 claims
- 0298US6433579B1Programmable logic integrated circuit devices with differential signaling capabilitiesALTERA CORP·Filed 2001·Granted Aug 13, 2002·136 cites·50 claims
- 0396US9711189B1On-die input reference voltage with self-calibrating duty cycle correctionWANG BONNIE I·Filed 2011·Granted Jul 18, 2017·37 cites·12 claims
- 0496US7593273B2Read-leveling implementations for DDR3 applications on an FPGAALTERA CORP·Filed 2007·Granted Sep 22, 2009·44 cites·22 claims
- 0596US7590008B1PVT compensated auto-calibration scheme for DDR3ALTERA CORP·Filed 2007·Granted Sep 15, 2009·58 cites·25 claims
- 0695US7983094B1PVT compensated auto-calibration scheme for DDR3ALTERA CORP·Filed 2009·Granted Jul 19, 2011·49 cites·20 claims
- 0795US7227395B1High-performance memory interface circuit architectureALTERA CORP·Filed 2005·Granted Jun 5, 2007·22 cites·29 claims
- 0895US7167023B1Multiple data rate interface architectureALTERA CORP·Filed 2005·Granted Jan 23, 2007·20 cites·47 claims
- 0994US10145868B2Self-referenced on-die voltage droop detectorAMPERE COMPUTING LLC·Filed 2016·Granted Dec 4, 2018·7 cites·18 claims
- 1094US6911860B1On/off reference voltage switch for multiple I/O standardsALTERA CORP·Filed 2001·Granted Jun 28, 2005·59 cites·26 claims
- 1193US8565034B1Variation compensation circuitry for memory interfaceLU SEAN SHAU-TU·Filed 2011·Granted Oct 22, 2013·31 cites·20 claims
- 1292US10162373B1Variation immune on-die voltage droop detectorAMPERE COMPUTING LLC·Filed 2017·Granted Dec 25, 2018·11 cites·20 claims
- 1392US8922264B1Methods and apparatus for clock tree phase alignmentALTERA CORP·Filed 2013·Granted Dec 30, 2014·12 cites·19 claims
- 1492US8593195B1High performance memory interface circuit architectureHUANG JOSEPH·Filed 2012·Granted Nov 26, 2013·8 cites·14 claims
- 1592US6825692B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2002·Granted Nov 30, 2004·38 cites·25 claims
- 1692US6806733B1Multiple data rate interface architectureALTERA CORP·Filed 2002·Granted Oct 19, 2004·48 cites·16 claims
- 1791US7884619B1Method and apparatus for minimizing skew between signalsALTERA CORP·Filed 2009·Granted Feb 8, 2011·17 cites·7 claims
- 1891US7425844B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2007·Granted Sep 16, 2008·14 cites·24 claims
- 1991US6870413B1Schmitt trigger circuit with adjustable trip point voltagesALTERA CORP·Filed 2001·Granted Mar 22, 2005·47 cites·25 claims
- 2090US8787097B1Circuit design technique for DQS enable/disable calibrationCHONG YAN·Filed 2011·Granted Jul 22, 2014·14 cites·19 claims
- 2190US7671579B1Method and apparatus for quantifying and minimizing skew between signalsALTERA CORP·Filed 2006·Granted Mar 2, 2010·16 cites·20 claims
- 2290US7002384B1Loop circuitry with low-pass noise filterALTERA CORP·Filed 2004·Granted Feb 21, 2006·38 cites·36 claims
- 2390US6630844B1Supply voltage detection circuitALTERA CORP·Filed 2001·Granted Oct 7, 2003·33 cites·37 claims
- 2489US8816743B1Clock structure with calibration circuitryALTERA CORP·Filed 2013·Granted Aug 26, 2014·11 cites·20 claims
- 2589US6766505B1Parallel programming of programmable logic using register chainsALTERA CORP·Filed 2002·Granted Jul 20, 2004·39 cites·29 claims
- 2689US6661733B1Dual-port SRAM in a programmable logic deviceALTERA CORP·Filed 2001·Granted Dec 9, 2003·39 cites·33 claims
- 2788US9106230B1Input-output circuitry for integrated circuitsALTERA CORP·Filed 2013·Granted Aug 11, 2015·8 cites·20 claims
- 2888US7928770B1I/O block for high performance memory interfacesALTERA CORP·Filed 2007·Granted Apr 19, 2011·22 cites·21 claims
- 2988US7746134B1Digitally controlled delay-locked loopsALTERA CORP·Filed 2007·Granted Jun 29, 2010·20 cites·18 claims
- 3087US8624647B2Duty cycle correction circuit for memory interfaces in integrated circuitsCHONG YAN·Filed 2010·Granted Jan 7, 2014·9 cites·20 claims
- 3187US8575957B2Multiple data rate interface architecturePAN PHILIP·Filed 2011·Granted Nov 5, 2013·5 cites·18 claims
- 3287US7893739B1Techniques for providing multiple delay paths in a delay circuitALTERA CORP·Filed 2009·Granted Feb 22, 2011·13 cites·22 claims
- 3387US7509223B2Read-side calibration for data interfaceALTERA CORP·Filed 2007·Granted Mar 24, 2009·15 cites·23 claims
- 3486US8237475B1Techniques for generating PVT compensated phase offset to improve accuracy of a locked loopNAGARAJAN PRADEEP·Filed 2008·Granted Aug 7, 2012·16 cites·25 claims
- 3586US7309906B1Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devicesALTERA CORP·Filed 2005·Granted Dec 18, 2007·13 cites·15 claims
- 3685US7215143B1Input buffer for multiple differential I/O standardsALTERA CORP·Filed 2004·Granted May 8, 2007·20 cites·30 claims
- 3785US7205806B2Loop circuitry with low-pass noise filterALTERA CORP·Filed 2005·Granted Apr 17, 2007·12 cites·18 claims
- 3884US8847626B1Circuits and methods for providing clock signalsALTERA CORP·Filed 2013·Granted Sep 30, 2014·6 cites·21 claims
- 3983US8098082B1Multiple data rate interface architecturePAN PHILIP·Filed 2010·Granted Jan 17, 2012·4 cites·20 claims
- 4082US9166589B2Multiple data rate interface architectureALTERA CORP·Filed 2013·Granted Oct 20, 2015·3 cites·17 claims
- 4182US9166596B2Memory interface circuitry with improved timing marginsALTERA CORP·Filed 2012·Granted Oct 20, 2015·6 cites·18 claims
- 4282US6946872B1Multiple data rate interface architectureALTERA CORP·Filed 2003·Granted Sep 20, 2005·24 cites·22 claims
- 4381US7330051B1Innovated technique to reduce memory interface write mode SSN in FPGAALTERA CORP·Filed 2006·Granted Feb 12, 2008·9 cites·20 claims
- 4480US9158873B1Circuit design technique for DQS enable/disable calibrationALTERA CORP·Filed 2014·Granted Oct 13, 2015·5 cites·19 claims
- 4580US7706996B2Write-side calibration for data interfaceALTERA CORP·Filed 2007·Granted Apr 27, 2010·10 cites·25 claims
- 4680US7492185B1Innovated technique to reduce memory interface write mode SSN in FPGAALTERA CORP·Filed 2007·Granted Feb 17, 2009·8 cites·21 claims
- 4778US6549045B1Circuit for providing clock signals with low skewALTERA CORP·Filed 2002·Granted Apr 15, 2003·22 cites·31 claims
- 4877US8122275B2Write-leveling implementation in programmable logic devicesCHONG YAN·Filed 2007·Granted Feb 21, 2012·9 cites·20 claims
- 4977US7200769B1Self-compensating delay chain for multiple-date-rate interfacesALTERA CORP·Filed 2002·Granted Apr 3, 2007·17 cites·35 claims
- 5076US7231536B1Control circuit for self-compensating delay chain for multiple-data-rate interfacesALTERA CORP·Filed 2004·Granted Jun 12, 2007·16 cites·16 claims
Showing the top 50 of 90 patent records by PatentIndex Score.
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