Inventor · disambiguated record
Devendra Deshpande
Also filed as: DESHPANDE DEVENDRA RAMAKANT · Deshpande Devendra
10 granted patents·238 citations·filing 2008–2021
87Inventor score
Files withCADENCE DESIGN SYSTEMS INC10
Top patents by PatentIndex Score
10 records- 0195US7917877B2System and method for circuit schematic generationCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Mar 29, 2011·199 cites·24 claims
- 0290US9830417B1Methods and systems for generation and editing of parameterized figure groupCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 28, 2017·14 cites·19 claims
- 0389US9842183B1Methods and systems for enabling concurrent editing of electronic circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 12, 2017·12 cites·19 claims
- 0486US10223495B1System and method for tuning a graphical highlight set to improve hierarchical layout awareness and editingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 5, 2019·5 cites·20 claims
- 0584US10671793B1Editing of layout designs for fixing DRC violationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 2, 2020·5 cites·20 claims
- 0674US10354034B1System and method for tuning a graphical highlight set to improve hierarchical layout editingCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 16, 2019·2 cites·20 claims
- 0766US11017145B1System and method for repeating a synchronized set of layout geometriesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 25, 2021·1 cites·20 claims
- 0853US11790149B1System and method for tracing nets across multiple fabrics in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 17, 2023·0 cites·20 claims
- 0948US12223244B1System and method for interactive visualization of placement of objects in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Feb 11, 2025·0 cites·20 claims
- 1044US10963616B1Systems and methods of aligning sets of wires with minimum spacing rulesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Mar 30, 2021·0 cites·20 claims
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