Inventor · disambiguated record
Pete D. Vogt
Also filed as: VOGT PETE · VOGT PETE D
62 granted patents·12 pending applications·1,458 citations·filing 1996–2024
99Inventor score
Top patents by PatentIndex Score
74 records- 0199US6316980B1Calibrating data strobe signal using adjustable delays with feedbackINTEL CORP·Filed 2000·Granted Nov 13, 2001·142 cites·24 claims
- 0297US6622227B2Method and apparatus for utilizing write buffers in memory control/interfaceINTEL CORP·Filed 2000·Granted Sep 16, 2003·187 cites·34 claims
- 0396US7165153B2Memory channel with unidirectional linksINTEL CORP·Filed 2003·Granted Jan 16, 2007·116 cites·45 claims
- 0495US9818457B1Extended platform with additional memory module slots per CPU socketINTEL CORP·Filed 2016·Granted Nov 14, 2017·12 cites·24 claims
- 0594US10146711B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2016·Granted Dec 4, 2018·14 cites·27 claims
- 0694US7383399B2Method and apparatus for memory compressionINTEL CORP·Filed 2004·Granted Jun 3, 2008·59 cites·7 claims
- 0793US6901494B2Memory control translatorsINTEL CORP·Filed 2003·Granted May 31, 2005·83 cites·25 claims
- 0892US7219294B2Early CRC delivery for partial frameINTEL CORP·Filed 2003·Granted May 15, 2007·73 cites·20 claims
- 0991US7702874B2Memory device identificationINTEL CORP·Filed 2005·Granted Apr 20, 2010·21 cites·17 claims
- 1091US7143207B2Data accumulation between data path having redrive circuit and memory deviceINTEL CORP·Filed 2003·Granted Nov 28, 2006·58 cites·21 claims
- 1190US7447953B2Lane testing with variable mappingINTEL CORP·Filed 2003·Granted Nov 4, 2008·59 cites·30 claims
- 1290US7212423B2Memory agent core clock aligned to laneINTEL CORP·Filed 2004·Granted May 1, 2007·49 cites·25 claims
- 1390US7194581B2Memory channel with hot add/removeINTEL CORP·Filed 2003·Granted Mar 20, 2007·59 cites·20 claims
- 1489US7650558B2Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systemsINTEL CORP·Filed 2005·Granted Jan 19, 2010·20 cites·13 claims
- 1588US9627357B2Stacked memory allowing variance in device interconnectsSHOEMAKER KENNETH·Filed 2011·Granted Apr 18, 2017·11 cites·12 claims
- 1686US8135999B2Disabling outbound drivers for a last memory buffer on a memory channelMORROW WARREN·Filed 2010·Granted Mar 13, 2012·7 cites·4 claims
- 1786US7386768B2Memory channel with bit lane fail-overINTEL CORP·Filed 2003·Granted Jun 10, 2008·29 cites·4 claims
- 1886US2024379625A1Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 1985US7127629B2Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signalINTEL CORP·Filed 2003·Granted Oct 24, 2006·40 cites·20 claims
- 2084US9652170B2Memory device responding to device commands for operational controlsINTEL CORP·Filed 2015·Granted May 16, 2017·3 cites·23 claims
- 2183US7464241B2Memory transaction burst operation and memory components supporting temporally multiplexed error correction codingINTEL CORP·Filed 2004·Granted Dec 9, 2008·33 cites·8 claims
- 2283US7343458B2Memory channel with unidirectional linksINTEL CORP·Filed 2006·Granted Mar 11, 2008·10 cites·20 claims
- 2383US7268020B2Embedded heat spreaderINTEL CORP·Filed 2007·Granted Sep 11, 2007·9 cites·10 claims
- 2482US10031802B2Embedded ECC address mappingINTEL CORP·Filed 2013·Granted Jul 24, 2018·6 cites·22 claims
- 2580US7369634B2Training pattern for a biased clock recovery tracking loopINTEL CORP·Filed 2004·Granted May 6, 2008·27 cites·13 claims
- 2679US10216657B2Extended platform with additional memory module slots per CPU socket and configured for increased performanceINTEL CORP·Filed 2016·Granted Feb 26, 2019·2 cites·25 claims
- 2779US8489944B2Disabling outbound drivers for a last memory buffer on a memory channelMORROW WARREN·Filed 2012·Granted Jul 16, 2013·4 cites·15 claims
- 2879US8020056B2Memory channel with bit lane fail-overINTEL CORP·Filed 2010·Granted Sep 13, 2011·4 cites·11 claims
- 2979US7200787B2Memory channel utilizing permuting status patternsINTEL CORP·Filed 2003·Granted Apr 3, 2007·24 cites·32 claims
- 3077US7761753B2Memory channel with bit lane fail-overINTEL CORP·Filed 2008·Granted Jul 20, 2010·4 cites·19 claims
- 3176US7827462B2Combined command and data codeINTEL CORP·Filed 2005·Granted Nov 2, 2010·7 cites·13 claims
- 3275US10249597B2Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystemsINTEL CORP·Filed 2016·Granted Apr 2, 2019·3 cites·28 claims
- 3374US7516349B2Synchronized memory channels with unidirectional linksINTEL CORP·Filed 2005·Granted Apr 7, 2009·6 cites·17 claims
- 3474US6049847ASystem and method for maintaining memory coherency in a computer system having multiple system busesCOROLLARY INC·Filed 1999·Granted Apr 11, 2000·75 cites·9 claims
- 3574US5897656ASystem and method for maintaining memory coherency in a computer system having multiple system busesCOROLLARY INC·Filed 1996·Granted Apr 27, 1999·66 cites·43 claims
- 3672US7395485B2Check codes mapped across multiple framesINTEL CORP·Filed 2004·Granted Jul 1, 2008·14 cites·9 claims
- 3771US10592445B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2018·Granted Mar 17, 2020·2 cites·31 claims
- 3870US8098783B2Training pattern for a biased clock recovery tracking loopPANIKKAR ADARSH·Filed 2008·Granted Jan 17, 2012·5 cites·11 claims
- 3969US10509738B2Remote memory operationsINTEL CORP·Filed 2016·Granted Dec 17, 2019·1 cites·23 claims
- 4069US8510612B2Disabling outbound drivers for a last memory buffer on a memory channelVOGT PETE D·Filed 2012·Granted Aug 13, 2013·1 cites·9 claims
- 4169US7340537B2Memory channel with redundant presence detectINTEL CORP·Filed 2003·Granted Mar 4, 2008·16 cites·19 claims
- 4268US10339072B2Read delivery for memory subsystem with narrow bandwidth repeater channelINTEL CORP·Filed 2016·Granted Jul 2, 2019·1 cites·26 claims
- 4368US9223718B2Memory device responding to device commands for operational controlsVOGT PETE·Filed 2012·Granted Dec 29, 2015·2 cites·24 claims
- 4466US7366931B2Memory modules that receive clock information and are placed in a low power stateINTEL CORP·Filed 2004·Granted Apr 29, 2008·13 cites·22 claims
- 4566US6622214B1System and method for maintaining memory coherency in a computer system having multiple system busesINTEL CORP·Filed 1999·Granted Sep 16, 2003·41 cites·9 claims
- 4665US7243205B2Buffered memory module with implicit to explicit memory command expansionINTEL CORP·Filed 2003·Granted Jul 10, 2007·11 cites·15 claims
- 4765US7111124B2Set partitioning for cache memoriesINTEL CORP·Filed 2002·Granted Sep 19, 2006·10 cites·16 claims
- 4864US8971087B2Stacked memory with interface providing offset interconnectsVOGT PETE·Filed 2011·Granted Mar 3, 2015·1 cites·21 claims
- 4963US12046577B2Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2019·Granted Jul 23, 2024·0 cites·20 claims
- 5060US8843794B2Method, system and apparatus for evaluation of input/output buffer circuitryNELSON CHRISTOPHER J·Filed 2012·Granted Sep 23, 2014·1 cites·30 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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