Inventor · disambiguated record
Jesse Peter Surprise
Also filed as: SURPRISE JESSE · SURPRISE JESSE P · SURPRISE JESSE PETER
14 granted patents·3 pending applications·25 citations·filing 2015–2023
87Inventor score
Files withIBM17
Top patents by PatentIndex Score
17 records- 0188US10902175B1Cross-hierarchical block pin placementIBM·Filed 2019·Granted Jan 26, 2021·8 cites·20 claims
- 0288US9684756B1Assigning nets to wiring planes using zero wire load and signal propagation timing for chip designIBM·Filed 2016·Granted Jun 20, 2017·9 cites·1 claims
- 0379US10943051B1Metal fill shape removal from selected netsIBM·Filed 2019·Granted Mar 9, 2021·4 cites·20 claims
- 0477US11720732B2Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specificationsIBM·Filed 2021·Granted Aug 8, 2023·1 cites·20 claims
- 0576US9934341B2Simulation of modifications to microprocessor designIBM·Filed 2015·Granted Apr 3, 2018·2 cites·10 claims
- 0661US10719654B2Placement and timing aware wire taggingIBM·Filed 2017·Granted Jul 21, 2020·1 cites·14 claims
- 0756US11797740B2Even apportionment based on positive timing slack thresholdIBM·Filed 2022·Granted Oct 24, 2023·0 cites·20 claims
- 0854US11775730B2Hierarchical large block synthesis (HLBS) fillingIBM·Filed 2021·Granted Oct 3, 2023·0 cites·20 claims
- 0954US10943040B1Clock gating latch placementIBM·Filed 2019·Granted Mar 9, 2021·0 cites·20 claims
- 1053US10902178B1Wire orientation-based latch shuddlingIBM·Filed 2019·Granted Jan 26, 2021·0 cites·20 claims
- 1153US9928322B2Simulation of modifications to microprocessor designIBM·Filed 2016·Granted Mar 27, 2018·0 cites·18 claims
- 1251US10831967B1Local clock buffer controller placement and connectivityIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 1349US12367331B2Approach to child block pinningIBM·Filed 2022·Granted Jul 22, 2025·0 cites·20 claims
- 1449US2025124205A1Content-aware apportionment of estimated timing slackIBM·Filed 2023·Application pending·0 cites
- 1545US2024086608A1Workload aware exerciser device placementIBM·Filed 2022·Application pending·0 cites
- 1644US2023244847A1New release process including consistency checkingIBM·Filed 2022·Application pending·0 cites
- 1742US10042972B2Assigning nets to wiring planes using zero wire load and signal propagation timing for chip designIBM·Filed 2017·Granted Aug 7, 2018·0 cites·1 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →