Inventor · disambiguated record
Jon K. Kriegel
Also filed as: KRIEGEL JON K
27 granted patents·7 pending applications·385 citations·filing 2004–2021
96Inventor score
Top patents by PatentIndex Score
34 records- 0196US8726295B2Network on chip with an I/O acceleratorIBM·Filed 2013·Granted May 13, 2014·40 cites·18 claims
- 0296US8438578B2Network on chip with an I/O acceleratorHOOVER RUSSELL D·Filed 2008·Granted May 7, 2013·47 cites·18 claims
- 0395US8490110B2Network on chip with a low latency, high bandwidth application messaging interconnectHOOVER RUSSELL D·Filed 2008·Granted Jul 16, 2013·49 cites·16 claims
- 0492US7913010B2Network on chip with a low latency, high bandwidth application messaging interconnectIBM·Filed 2008·Granted Mar 22, 2011·31 cites·16 claims
- 0591US8429377B2Optimizing TLB entries for mixed page size storage in contiguous memoryCHEN DONG·Filed 2010·Granted Apr 23, 2013·14 cites·20 claims
- 0690US7818503B2Method and apparatus for memory utilizationIBM·Filed 2006·Granted Oct 19, 2010·17 cites·20 claims
- 0789US10318435B2Ensuring forward progress for nested translations in a memory management unitIBM·Filed 2017·Granted Jun 11, 2019·6 cites·13 claims
- 0888US7552236B2Routing interrupts in a multi-node systemIBM·Filed 2005·Granted Jun 23, 2009·21 cites·13 claims
- 0988US7089341B2Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platformIBM·Filed 2004·Granted Aug 8, 2006·54 cites·21 claims
- 1087US8205067B2Context switching and synchronizationKRIEGEL JON K·Filed 2010·Granted Jun 19, 2012·11 cites·20 claims
- 1186US11422947B2Determining page size via page table cacheIBM·Filed 2020·Granted Aug 23, 2022·2 cites·20 claims
- 1285US8688953B2Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entitiesFRANKE HUBERTUS·Filed 2012·Granted Apr 1, 2014·8 cites·23 claims
- 1385US7752413B2Method and apparatus for communicating between threadsIBM·Filed 2006·Granted Jul 6, 2010·11 cites·24 claims
- 1485US7305524B2Snoop filter directory mechanism in coherency shared memory systemIBM·Filed 2004·Granted Dec 4, 2007·37 cites·5 claims
- 1582US7681020B2Context switching and synchronizationIBM·Filed 2007·Granted Mar 16, 2010·10 cites·18 claims
- 1681US8856490B2Optimizing TLB entries for mixed page size storage in contiguous memoryCHEN DONG·Filed 2012·Granted Oct 7, 2014·5 cites·22 claims
- 1778US8275971B2Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entitiesFRANKE HUBERTUS·Filed 2008·Granted Sep 25, 2012·8 cites·20 claims
- 1876US8296547B2Loading entries into a TLB in hardware via indirect TLB entriesHEIL TIMOTHY H·Filed 2009·Granted Oct 23, 2012·8 cites·15 claims
- 1972US8230179B2Administering non-cacheable memory load instructionsKRIEGEL JON K·Filed 2008·Granted Jul 24, 2012·5 cites·18 claims
- 2055US11734188B2Unified translation miss queue for multiple address translation modesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·24 claims
- 2155US10380031B2Ensuring forward progress for nested translations in a memory management unitIBM·Filed 2017·Granted Aug 13, 2019·0 cites·7 claims
- 2254US2018300256A1Maintaining agent inclusivity within a distributed mmuIBM·Filed 2017·Application pending·0 cites
- 2353US2018300255A1Maintaining agent inclusivity within a distributed mmuIBM·Filed 2017·Application pending·0 cites
- 2452US11636043B2Sleeping and waking-up address translation that conflicts with translation level of active page table walksIBM·Filed 2021·Granted Apr 25, 2023·0 cites·20 claims
- 2552US11556475B2Power optimized prefetching in set-associative translation lookaside buffer structureIBM·Filed 2021·Granted Jan 17, 2023·0 cites·14 claims
- 2651US2007294481A1Snoop filter directory mechanism in coherency shared memory systemHOOVER RUSSELL D·Filed 2007·Application pending·0 cites
- 2750US7577794B2Low latency coherency protocol for a multi-chip multiprocessor systemIBM·Filed 2004·Granted Aug 18, 2009·1 cites·5 claims
- 2848US2012215988A1Administering Non-Cacheable Memory Load InstructionsKRIEGEL JON K·Filed 2012·Application pending·0 cites
- 2947US8826299B2Spawned message state determinationKRIEGEL JON K·Filed 2007·Granted Sep 2, 2014·0 cites·19 claims
- 3047US7840757B2Method and apparatus for providing high speed memory for a processing unitIBM·Filed 2004·Granted Nov 23, 2010·0 cites·20 claims
- 3147US2009125706A1Software Pipelining on a Network on ChipHOOVER RUSSELL D·Filed 2007·Application pending·0 cites
- 3246US11221957B2Promotion of ERAT cache entriesIBM·Filed 2018·Granted Jan 11, 2022·0 cites·18 claims
- 3346US2006080511A1Enhanced bus transactions for efficient support of a remote cache directory copyIBM·Filed 2004·Application pending·0 cites
- 3446US2009049272A1Method for improving the performance of software-managed tlbIBM·Filed 2007·Application pending·0 cites
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