Inventor · disambiguated record
Ruth A. Brain
Also filed as: BRAIN RUTH · BRAIN RUTH A · BRAIN RUTH AMY
39 granted patents·6 pending applications·339 citations·filing 1995–2023
97Inventor score
Top patents by PatentIndex Score
45 records- 0194US6958547B2Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugsINTEL CORP·Filed 2003·Granted Oct 25, 2005·71 cites·19 claims
- 0293US10032643B2Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner schemeINTEL CORP·Filed 2014·Granted Jul 24, 2018·16 cites·25 claims
- 0393US8143159B2Fabrication of interconnects in a low-k interlayer dielectricsKING SEAN·Filed 2010·Granted Mar 27, 2012·17 cites·17 claims
- 0493US7008872B2Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structuresINTEL CORP·Filed 2002·Granted Mar 7, 2006·59 cites·16 claims
- 0589US9899255B2Via blocking layerINTEL CORP·Filed 2014·Granted Feb 20, 2018·8 cites·25 claims
- 0686US11145541B2Conductive via and metal line end fabrication and structures resulting therefromINTEL CORP·Filed 2017·Granted Oct 12, 2021·5 cites·18 claims
- 0784US10943817B2Etch-stop layer topography for advanced integrated circuit structure fabricationINTEL CORP·Filed 2019·Granted Mar 9, 2021·3 cites·18 claims
- 0884US10468298B2Decoupled via fillINTEL CORP·Filed 2019·Granted Nov 5, 2019·3 cites·20 claims
- 0983US10796951B2Etch-stop layer topography for advanced integrated circuit structure fabricationINTEL CORP·Filed 2017·Granted Oct 6, 2020·3 cites·17 claims
- 1082US9607992B2Etchstop layers and capacitorsINTEL CORP·Filed 2016·Granted Mar 28, 2017·2 cites·20 claims
- 1181US10026649B2Decoupled via fillINTEL CORP·Filed 2014·Granted Jul 17, 2018·4 cites·20 claims
- 1280US10811595B2Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memoryINTEL CORP·Filed 2016·Granted Oct 20, 2020·2 cites·21 claims
- 1380US7812455B2Interconnect in low-k interlayer dielectricsINTEL CORP·Filed 2008·Granted Oct 12, 2010·8 cites·6 claims
- 1478US8058177B2Winged vias to increase overlay marginWEISS MARTIN·Filed 2008·Granted Nov 15, 2011·11 cites·7 claims
- 1577US11068640B2Power shared cell architectureINTEL CORP·Filed 2017·Granted Jul 20, 2021·3 cites·25 claims
- 1677US8933564B2Landing structure for through-silicon viaPELTO CHRISTOPHER M·Filed 2012·Granted Jan 13, 2015·6 cites·27 claims
- 1773US6048445AMethod of forming a metal line utilizing electroplatingINTEL CORP·Filed 1998·Granted Apr 11, 2000·34 cites·30 claims
- 1872US9054068B2Etchstop layers and capacitorsBRAIN RUTH A·Filed 2011·Granted Jun 9, 2015·2 cites·24 claims
- 1971US11322504B2Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technologyINTEL CORP·Filed 2018·Granted May 3, 2022·1 cites·25 claims
- 2071US5707466AMethod and apparatus for selectively annealing heterostructures using microwaveCALIFORNIA INST OF TECHN·Filed 1995·Granted Jan 13, 1998·34 cites·21 claims
- 2169US12308284B2Plug and trench architectures for integrated circuits and methods of manufactureINTEL CORP·Filed 2021·Granted May 20, 2025·0 cites·19 claims
- 2269US6774037B2Method integrating polymeric interlayer dielectric in integrated circuitsINTEL CORP·Filed 2002·Granted Aug 10, 2004·18 cites·22 claims
- 2361US10903114B2Decoupled via fillINTEL CORP·Filed 2019·Granted Jan 26, 2021·0 cites·20 claims
- 2459US11652045B2Via contact patterning method to increase edge placement error marginINTEL CORP·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 2559US10032857B2Etchstop layers and capacitorsINTEL CORP·Filed 2017·Granted Jul 24, 2018·0 cites·21 claims
- 2657US10672650B2Via blocking layerINTEL CORP·Filed 2018·Granted Jun 2, 2020·0 cites·20 claims
- 2757US10593626B2AVD hardmask for damascene patterningINTEL CORP·Filed 2017·Granted Mar 17, 2020·0 cites·24 claims
- 2857US10211098B2Decoupled via fillINTEL CORP·Filed 2018·Granted Feb 19, 2019·0 cites·20 claims
- 2957US9343524B2Etchstop layers and capacitorsINTEL CORP·Filed 2015·Granted May 17, 2016·0 cites·21 claims
- 3057US5851319AMethod and apparatus for selectively annealing heterostructures using microwavesCALIFORNIA INST OF TECHN·Filed 1997·Granted Dec 22, 1998·18 cites·4 claims
- 3156US9780038B2AVD hardmask for damascene patterningINTEL CORP·Filed 2016·Granted Oct 3, 2017·0 cites·12 claims
- 3252US11211324B2Via contact patterning method to increase edge placement error marginINTEL CORP·Filed 2019·Granted Dec 28, 2021·0 cites·20 claims
- 3351US11171043B2Plug and trench architectures for integrated circuits and methods of manufactureINTEL CORP·Filed 2016·Granted Nov 9, 2021·0 cites·13 claims
- 3451US2015137368A1Landing structure for through-silicon viaINTEL CORP·Filed 2014·Application pending·0 cites
- 3549US9502281B2AVD hardmask for damascene patterningBRAIN RUTH A·Filed 2011·Granted Nov 22, 2016·0 cites·15 claims
- 3648US11764219B2Metal space centered standard cell architecture to enable higher cell densityINTEL CORP·Filed 2019·Granted Sep 19, 2023·0 cites·25 claims
- 3748US2025006721A1Cell rows with mixed heights and mixed nanoribbon widthsINTEL CORP·Filed 2023·Application pending·0 cites
- 3846US10535601B2Via blocking layerINTEL CORP·Filed 2016·Granted Jan 14, 2020·0 cites·20 claims
- 3944US11723188B2Replacement metal COB integration process for embedded DRAMINTEL CORP·Filed 2018·Granted Aug 8, 2023·0 cites·16 claims
- 4044US6365514B1Two chamber metal reflow processINTEL CORP·Filed 1997·Granted Apr 2, 2002·11 cites·26 claims
- 4141US2021183761A1Line patterning in integrated circuit devicesINTEL CORP·Filed 2019·Application pending·0 cites
- 4240US11417567B2Conductive cap-based approaches for conductive via fabrication and structures resulting therefromINTEL CORP·Filed 2016·Granted Aug 16, 2022·0 cites·23 claims
- 4339US2014002976A1Recessed bottom-electrode capacitors and methods of assembling sameBRAIN RUTH A·Filed 2011·Application pending·0 cites
- 4437US2014001598A1Atomic layer deposition (ald) of taalc for capacitor integrationLINDERT NICK·Filed 2011·Application pending·0 cites
- 4536US2019013353A1Approaches for integrating stt-mram memory arrays into a logic processor and the resulting structuresINTEL CORP·Filed 2016·Application pending·0 cites
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